Scales and Dimensions of Integration
In this article, the author analyze modern electronic integration technology from two aspects: Scale and Dimension.
Integration refers to the process of bringing different units together to achieve their specific functions. Integration mostly refers to human activities rather than natural processes.
Integrated circuits and system integration are common terms.
Today, the two major directions for the development of integrated circuits are: smaller scale and higher dimension.
The article was first published on February 14, 2022, and was republished today with some corrections.
Scales of Integration
Scale is generally understood as size, measured length, and prescribed limits, which can be extended to standards and procedures. In this article, scale refers to the size of the object being described.
Analyze the scales of integration in order from small to large. Let’s start with the smallest elementary particles.
Elementray Particles
The world known to mankind is composed of 61 elementary particles.
These elementary particles are divided into three categories: quark, lepton, and boson.
Among them, only electron, photon and neutrino are particles that stably exist in nature and can affect the macroscopic world.
The famous quarks are imprisoned in composite particles such as protons and neutrons and cannot be released for life.
Electron (lepton): Electrons are the most fully understood and most widely used elementary particle by humans. Today, modern technology basically revolves around electronics. Without electronics, the entire world would come to a standstill.
Photon (boson): The application of photons is earlier than that of electrons. It has been used since ancient times. In modern times, photons are inseparable from daily life to the latest scientific fields.
Neutrino (lepton): Neutrinos are difficult to detect, so they are called mysterious particles. Although they have few applications at present, they are regarded as a type of particle with great potential. It is extremely fast, close to the speed of light, and can pass through all objects without hindrance. In the future, it can be used in neutrino communications, stratigraphy scanning and other fields.
And those elementary particles that cannot exist independently in nature cannot directly interact with the macroscopic world, so their impacts on human beings are far less than electrons, photons and neutrinos.
Atoms
We scale up to atoms.
Of the 118 elements currently known to humans, 92 come from nature, and the rest are artificially synthesized. The smallest unit representing an element is called an atom, and different atoms constitute different substances.
The structure of an atom. An atom consists of a nucleus and electrons orbiting the nucleus. The nucleus occupies only a few hundred billionths of the volume of the atom, so the volume of the atom is determined by the electrons outside the nucleus.
Electrons have wave-particle duality. They do not have a definite orbit like the movement of macroscopic objects. It is impossible to predict where in the extranuclear space it will appear at a certain moment. We only know the probability of it appearing somewhere. It is like a negatively charged cloud that surrounds the atomic nucleus, so it is called an “electron cloud.”
Let’s take silicon, the most commonly used element in semiconductors, as an example.
There are 14 electrons outside the silicon nucleus, of which there are 2 electrons in the first layer, 8 electrons in the second layer, and the outermost 4 electrons are valence electrons.
There are no obvious free electrons in silicon crystals. The four outermost electrons of silicon atoms are neither as active as in conductors, nor as tightly bound as in insulators. Their activities are between conductors and insulators, have semiconductor properties. Silicon can conduct electricity, but its conductivity is not as good as metals and increases with temperature.
The scale of an atom. An atom does not have a precisely defined outermost layer. The atomic radius is usually measured based on the average nuclear distance between adjacent atoms. So, what is the distance between silicon atoms in a silicon crystal?
The most basic geometric unit that constitutes a crystal is called a Unit Cell. The Unit Cell of silicon crystal is a face cube. The side length of its Unit Cell is 0.543nm.
One face of the silicon atom Unit Cell is used as the plane. The silicon atoms are arranged as shown below. The minimum distance between silicon atoms in this plane is 0.384nm, and the arrangement width of three silicon atoms is 1.152nm.
So, how many silicon atoms are there in a cubic nanometer?
In a face cube unit cell composed of silicon atoms, there is one silicon atom at each of the 8 vertices and 6 faces. There are also 4 silicon atoms located at 1/4 of the diagonals of the four spaces. On average, the number of atoms in each silicon unit cell is 8 (8 × 1/8 + 6 × 1/2 + 4 = 8).
The unit cell side length of silicon is a (Lattice constant). At 300K, a=5.4305Å (0.543nm).
8 ÷ (0.54³³) = 49.97 ≈ 50, that is to say, the number of silicon atoms in 1nm³ is 50. Calculation based on the density of silicon material and the mass of silicon atoms will get the same result.
In order to improve the conductive properties of silicon, a small amount of 5-valent elements are mixed into it to form an N-type semiconductor, or a small amount of 3-valent elements are mixed into it to form a P-type semiconductor.
No matter what element is added, it will basically not change the lattice structure of silicon. Therefore, the distance between atoms will not change, and the number of atoms in 1nm³ will not change, still 50.
At the nanometer scale, atoms can also be counted by number.
From Atom to Function Cell
What is a Function Cell? We define it as the smallest unit of function. In an integrated circuit, a transistor can be defined as a Function Cell. Of course, resistors, capacitors, inductors, diodes, etc. are also function cells.
Function cells are composed of atoms, and the functions are realized by controlling electrons. It can also be said that the functions of function cells are given by electrons. If they can reasonably control electrons, they will have corresponding functions.
The realization of functions comes from practical needs, human wisdom and those great inventions or discoveries.
Let’s take the most typical Function Cell transistor in integrated circuits as an example.
The reason why transistors can become Function Cells lies in their ability to effectively control electrons.
The picture below shows the current mainstream FinFET transistor. By applying a reasonable voltage to the gate (Gate), electrons can flow from Source to Drain, thereby generating current and conducting.
Different states can be represented by turning on and off transistors. When multiple transistors are combined together, different logic circuits can be formed to complete different functions.
As long as they can perform the same function, the smaller the size of the Function Cells, the better. How small can Function Cells be?
For existing silicon-based transistors, they are generally restricted by two factors. One is the minimum structural width within the transistor, and the other is the area or volume occupied by the transistor itself.
From the above analysis, we know that the width of three silicon atoms arranged side by side exceeds 1nm. Is it possible that the minimum structural width of a transistor can reach or even be less than 1nm? It’s hard to make a conclusion now. Not only is it difficult to manufacture with such a small width, it is also difficult for transistors that work properly according to existing theories.
New types of transistors, such as single-atom transistors, have a minimum structural width of only one atom, and control the on and off of the transistor by operating a single atom.
It is said that the energy consumption of single-atom transistors will be only one ten thousandth (1/10000) of silicon-based transistors, which is a decisive advantage for future applications.
From Function Cell to Common System
Functional cells can be very small.
Current technology can support the integration of more than 10 billion transistors on a chip the size of a fingernail. Multiple Function Cells can form a Function Block, multiple Function Blocks form a Function Unit, and multiple Function Units form a MicroSystem.
However, for humans, the scale of their products needs to be suitable for human needs and must be equivalent to the scale of humans themselves.
For example, mobile phones and computers, the former need to be often held in the hand, so they need to be the same size as the human hand, while the latter need to be placed on the table or on the lap, so they are the same horizontal size as the human body.
This type of system is called a Common System, which means a system that ordinary people can access and use frequently. Common systems are composed of Microsystems, Function units, and ultimately Function cells.
Because Common systems need to match human scales, no matter how advanced science and technology develops, their scales will not change too much. However, in order to meet more function needs of humans, the number of Function Cells they contain will continue to increase, that is, the system Function Density will continue to increase.
Moreover, in the process of the development of human civilization, this trend will continue, which is also in line with the description of the Function Density Law.
From Common System to Giant System
In addition, there is a type of system that, although it also serves people, does not serve individuals but serves groups, so its scale can be very large. We call this type of system Giant System. For example, manned spaceflight system, wireless communication network system, GPS global satellite positioning system, etc.
Giant Systems are usually very complex and generally consist of many Common systems, Microsystems or Function UNITs.
For example, GPS system is divided into three parts: the space part, which consists of a total of 24 satellites; the ground part, which consists of the main control station, monitoring station, and ground antenna; and the user equipment part, which is a variety of GPS signal receivers.
GPS system can perform real-time high-precision positioning, speed measurement and precise timing for various mobile users such as ground vehicles, ships, aircraft, satellites and spacecraft.
Giant systems, like Common systems, will continue to increase their Function Density in order to meet more function requirements, and this trend will continue with the development of human civilization. It also conforms to the description of Function Density Law.
Scale of Integration Summary
Here, we use two figures to summarize the scale of integration.
We divide electronic systems into 6 levels according to levels, which is called the 6-level classification of electronic systems, please see the author’s book “Microsystems Based on SiP Technology” for details.
Among them, Function cells are the smallest function UNITs, Function Cells → Function Blocks → Function Units, which are three different Function UNITs, and thus constitute Microsystem → Common System → Giant system, as shown in the figure below.
Then, we analyzed the Function cell and divided it into 4 levels according to the hierarchy: elementray particles make up atom, atoms form Unit Cell, and Unit Cells make up Function Cell.
In this article, from Elementary particles to the most complex systems currently achievable by humans, we divide them into 9 (4+6–1) levels according to scale.
Among them, Function Cells are the most critical level and the basic unit and carrier of function, just like cells in human body, are the constituent units of human life and the carriers of wisdom.
Each level requires different people to explore, realize, innovate, develop, and integrate human wisdom into it.
Dimensions of Integration
The world that humans can perceive has only three spatial dimensions, adding time, it is often called four-dimensional space-time.
Whether the 11-dimensional space-time described in string theory actually cannot be confirmed exists or not. Even if it exists, it is like those elementary particles that are imprisoned in the microscopic world and cannot be perceived in the human macroscopic world. Therefore, it has almost no impact on human activities.
In our general understanding, zero dimension is a point, one dimension is a line, two dimension is a plane, and three dimension is a solid.
Integration is the process of bringing different units together and realizing their specific functions. Therefore, zero-dimensional points and one-dimensional lines are not suitable for integration. In reality, the main integration methods are two-dimensional planar integration and Three-dimensional solid integration.
In practical applications, it is indeed difficult to classify integration using only two dimensions and three dimensions. For example, some people use “fake 3D” and “true 3D” to distinguish different types of chip stacking methods.
In this article, we divide integration into five integration dimensions: 2D, 2D+, 2.5D, 3D, and 4D. The purpose is to facilitate the classification and differentiation of integration, and is also compatible with the current mainstream statement.
Furthermore, we give two important criteria, Physical structure and Electrical interconnection.
The integration described below is mainly aimed at the field of integrated circuit packaging, and the same can be applied for other fields.
2D Integration
2D integration refers to an integration method in which all chips and passive components are mounted horizontally on the surface of the substrate.
Create a coordinate system with the lower left corner of the upper surface of the substrate as the origin, the plane on the upper surface of the substrate as the XY plane, and the normal line of the substrate as the Z axis.
Physical structure: All chips and passive devices are installed on the substrate plane. The chips and passive devices are in direct contact with the XY plane. The traces and vias on the substrate are located below the XY plane;
Electrical interconnections: all need to pass through the substrate (except for small number of bond pads directly connected by bond wires).
Most common 2D integration technology is used in MCM, some SiP and PCB.
MCM (Multi Chip Module) is a complete component that consists of multiple bare chips mounted on the same substrate at high density.
In the traditional packaging field, all packages are chip-oriented, serving the chip, protecting the chip, amplifying the scale and making electrical connections. There is no concept of integration.
With the rise of MCM, the concept of integration has emerged in packaging, so packaging has also undergone essential changes. MCM has shifted the concept of packaging from chips to modules, components or systems.
The process route of 2D integrated SiP is very similar to MCM. The main difference from MCM is that the scale of 2D integrated SiP is larger than that of MCM and it can form an independent system.
In addition, FOWLP-based integration, such as INFO, although there is no substrate, can also be attributed to 2D integration. At present, the arrangement of transistors in integrated circuits basically belongs to 2D integration.
2D integration is the simplest for EDA design tools. The figure below shows the 2D integrated design implemented in EDA tool.
2D+ Integration
2D+ integration refers to traditional chip stacking integration connected by bond wires. Some people may ask, isn’t chip stacking 3D? Why is it defined as 2D+ integration?
Mainly based on the following two reasons: 1) 3D integration currently refers to the integration through 3D TSV to a large extent. In order to avoid conceptual confusion, we define this traditional chip stack as 2D+ integration; 2) Although the physical structure is 3D , but the electrical interconnections need to pass through the substrate, that is, they are first bonded to the substrate through bond wires, and then electrically interconnected on the substrate.
This is the same as 2D integration. What is improved over 2D integration is the structural stacking, which can save packaging space, so it is called 2D+ integration.
Physical structure: All chips and passive devices are located above the XY plane. Some chips do not directly contact the substrate. The traces and vias on the substrate are located below the XY plane.
Electrical interconnections: all need to pass through the substrate, except for a few bond pads are directly connected by bond wires.
Several integrations shown in the figure below are all 2D+ integrations.
In addition, the integration method of PoP (Package on Package) can also be judged based on its physical structure and electrical connection, and it can be attributed to 2D+ integration.
EDA design tools have always had good support for 2D+ integration. The figure below shows the 2D+ integrated design implemented in EDA tool.
2.5D Integration
As the name suggests, 2.5D is between 2D and 3D. It usually refers to a dimension that has both the characteristics of 2D and some of the characteristics of 3D. In reality, there is no such dimension as 2.5D.
Physical structure: All chips and passive devices are above the XY plane, and at least some of the chips and passive devices are installed on the interposer. Above the XY plane, there are traces and vias of the interposer, and below the XY plane There are traces and vias on the substrate.
Electrical interconnection: The interposer provides electrical connections to the chips located on the interposer.
The key to 2.5D integration lies in the interposer. Generally, there are several situations: 1) whether the interposer uses a silicon adapter board, 2) whether the interposer uses TSV, 3) using other types of material adapter boards; in silicon adapter board, we call the via that passes through the interposer TSV, and for the glass adapter board, we call it TGV.
Integration with TSV in silicon interposer is the most common 2.5D integration technology. The chip is usually connected to the interposer through MicroBump. The silicon substrate as the interposer is connected to the substrate using Bump. The surface of the silicon substrate is routed through RDL. TSVs are used as channels for electrical connection between the upper and lower surfaces of the substrate.
This 2.5D integration is suitable for situations where the chip size is relatively large and the pin density is high. The chip is generally installed on the silicon substrate in the form of FlipChip.
The structure of 2.5D integration without TSV in the silicon interposer is generally as shown in the figure below. There is a large bare chip directly installed on the substrate. The connection between the chip and the substrate can be done in two ways: Bond Wire or Flip Chip. For large chips Due to the large area above, multiple smaller bare chips can be installed, but the small chips cannot be directly connected to the substrate, so an interposer needs to be inserted, and multiple bare chips are installed above the interposer.
There is RDL layer on the interposer. traces on RDL can lead the chip’s signal to the edge of the interposer, and then connect it to the substrate through Bond Wire. This type of interposer usually does not require TSV and only requires electrical interconnection through traces on the upper surface of the Interposer. The Interposer uses bond wires to connect to the package substrate.
Now, EDA design tools have good support for 2.5D integration. The figure below shows the 2.5D integrated design implemented in EDA tool.
3D Integration
The main difference between 3D integration and 2.5D integration is that 2.5D integration is routing and drilling on the interposer, while 3D integration is directly drilling (TSV) and routing (RDL) on the chip to electrically connect the upper and lower chips.
Physical structure: All chips and passive components are located above the XY plane, the chips are stacked together, there are TSVs passing through the chips above the XY plane, and there are traces and vias of the substrate below the XY plane.
Electrical interconnection: Direct electrical connections between chips via TSV and RDL.
Most applications of 3D integration are in homogeneous chip stacking, where multiple identical chips are vertically stacked together and interconnected by TSVs that pass through the chip stack, as shown in the figure below. Similar chip integration is mostly used in memory integration, such as DRAM Stack, FLASH Stack, etc.
In the 3D integration of different types of chips, two different chips are generally stacked vertically, electrically connected together through TSV, and interconnected with the substrate below.
Sometimes it is necessary to make RDL on the surface of the chip to connect the upper and lower TSVs.
In addition, the current 3D Nand Flash produces multi-layer memory cells directly on the chip, which is also a 3D integration technology.
Now, EDA design tools have good support for 3D integration. The figure below shows the 3D integrated design implemented in EDA tool.
4D Integration
We introduced 2D, 2D+, 2.5D, and 3D integration above. How is 4D integration defined?
In the several integrations introduced earlier, in the three-dimensional coordinate system, the Z-axis of all chips, interposers and substrates is vertically upward, that is, all substrates and chips are Installed in parallel. In 4D integration, this situation changes.
When the XY planes of different substrates are not parallel, that is, the Z-axis directions of different substrates are offset, we can define this type of integration as 4D integration.
Physical structure: Multiple substrates are installed in a non-parallel manner, and components are installed on each substrate. The installation methods of components are diverse.
Electrical interconnection: The substrates are connected through flexible circuits or welding, and the electrical connections of the chips on the substrate are diverse.
The definition of 4D integration is mainly about the orientation and interconnection methods of multiple substrates. Therefore, each substrate in 4D integration may include 2D, 2D+, 2.5D, and 3D integration methods.
4D integration technology can solve problems that cannot be solved by parallel three-dimensional stacking, provide more flexible chip installation space, solve the heat dissipation problem of high-power chips, and solve air tightness issues that are of concern in applications in aerospace and other fields.
Now, EDA design tools also have good support for 4D integration. The figure below shows the 4D integrated design implemented in EDA tool.
4D integration technology has improved the flexibility and diversification of integration. Looking to the future, 4D integration will definitely have a place in various integration dimensions and will become an important integration technology after 2D, 2D+, 2.5D and 3D integration technology.
In a strict physical sense, based on current human cognition, all objects are three-dimensional, two-dimensional foil does not exist, and four-dimensional space needs to be verified.
In order to easily distinguish between various integration methods, we divide them into five integration dimensions: 2D, 2D+, 2.5D, 3D, and 4D.
Dimensions of Integraton Summary
Here, we use a picture to summarize the integration dimensions. As shown in the figure below, it contains an EDA design legend of 5 integration dimensions and the specific integration types included in each dimension.
Summary
Integration generally refers to human activities rather than natural processes. Therefore, integration is also an important ways for humans to change the world.
In this article, the author analyze modern electronic integration technology from two aspects: scale and dimension. Both belong to the category of space, one represents the size of space, and the other represents the orientation of space.
The scale of integration is divided into 9 levels for description, from the smallest elementary particles to the most complex Giant systems; the dimension of integration defines 5 dimensions for classification and description.
This article provides a detailed description of the integration from the spatial axis.
Today, the two major directions for the development of integrated circuits are: smaller scale and higher dimension.
The two complement each other and jointly promote the development of human civilization.
Author’s Book
The book “Microsystem Based on SiP Technology” covers three parts: “Concept and Technology”, “Design and Simulation”, and “Project and Case”. It contains 30 chapters, with a total of about 1.1 million+ words, 1000+ illustrations, and about 890 pages.
This book is recommended for readers who are concerned about SiP, Advanced Packaging, Microsystem, and product miniaturization, low power consumption and high performance.