Page 1 CEM2100/00/98 11-12 13-14 15-16 TUNER PCB COMPONENT LAYOUT..........17-18 BOARD..........8 CD CONNECTOR PCB COMPONENT LAYOUT......20 CIRCUIT DIAGRAM TUNER BOARD........10 ........... 22 2011-6-29...
Page 3 BLOCK DIAGRAM...
Page 4 WIRING DIAGRAM...
Page 5: Board
CIRCUIT DIAGRAM -MAIN BOARD...
Page 8 CIRCUIT DIAGRAM -PANEL BOARD LCD901 LCD-68 R951 Q901 9014C R952 R931 IC901 C906 680P SC75823 C901 C902 C903 C904 C905 ZD903 ZD904 ZD901 ZD902 USB_GND CON901 R927 USB_DP R928 USB_DN C909 R929 USB_5V C910 C911 R930 C908 10UF USB_5V SYS_5V BT_LED LAMP_VCC R901...
Page 9 CIRCUIT DIAGRAM-REMOTE BOARD...
Page 10 CIRCUIT DIAGRAM-TUNER BOARD XT001 R014 C009 32.768KHz C008 R001 270K C001 L001 C004 Q001 C006 C003 R003 220NH L003 RFGND L002 C002 SK255 2.7UH 220NH IC001 LOUT R002 C005 CTUNE SI474X ROUT RF-GND L006 C017 33UH Q102/Q003 L004 L005 C013 C025 C007 FB152...
Page 11 PCB LAYOUT-MAIN BOARD TOP SIDE VIEW...
Page 12 PCB LAYOUT-MAIN BOARD BOTTOM SIDE VIEW...
Page 13 PCB LAYOUT -PANEL BOARD TOP SIDE VIEW...
Page 14 PCB LAYOUT -PANEL BOARD BOTTOM SIDE VIEW...
Page 15 PCB LAYOUT-REMOTE BOARD TOP SIDE VIEW...
Page 16 PCB LAYOUT-REMOTE BOARD BOTTOM SIDE VIEW...
Page 17 PCB LAYOUT -TUNER BOARD TOP SIDE VIEW...
Page 18 PCB LAYOUT -TUNER BOARD BOTTOM SIDE VIEW...
Page 19 PCB LAYOUT-SD BOARD TOP SIDE VIEW...
Page 20 PCB LAYOUT CD CONNECTOR TOP SIDE VIEW...
Page 21 PCB LAYOUT-ISO BOARD BOTTOM SIDE VIEW...
Page 22 SET EXPLODER VIEW DRAWING...
Page 23 CEM2100 1 of 2...
Page 24 CEM2100 Trouble shooting CEM2100 2011-11-14 Product Model Area Date failure cause remark failure phenomena a. To check whether it is connect well of the ISO connector (4PIN power input ). Whether it is loose of the 15A fuse of the ISO connector, or insert non in place b.
Page 25 failure cause remark failure phenomena a. To check whether the signal format of the disc is correspond to the request of the unit, whether there is any contamination or damage or light leakage on the surface of the disc b. To check whether there is any abnormal of the rotation of the deck mecahnism, or whether the disc is enter in position c.
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Page 111 8 Bit Microcontroller TLCS-870/C Series T5CL8...
Page 112 The information contained herein is subject to change without notice. 021023_D TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
Page 113 Revision History Date Revision 2008/7/31 First Release...
Page 115: Table Of Contents
Table of Contents Differences among Products T5CL8 Features ............1 Pin Assignment .
Page 116 3.3.2.2 Using data transfer instructions 3.3.3 Interrupt return ............................41 Software Interrupt (INTSW) ......... . 42 3.4.1 Address error detection ..........................
Page 117 8. 16-Bit TimerCounter 1 (TC1) Configuration ........... . 77 TimerCounter Control .
Page 118 (NORMAL1 → NORMAL2 → SLOW2 → SLOW1) 11.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 → SLOW2 → NORMAL2 → NORMAL1) 12. Asynchronous Serial interface (UART1 ) 12.1 Configuration ..........139 12.2 .
Page 119 14.3.2.2 Receive mode 14.3.2.3 Transmit/receive mode 14.3.3 Transfer modes........................... 165 14.3.3.1 Transmit mode 14.3.3.2 Receive mode 14.3.3.3 Transmit/receive mode 15. Synchronous Serial Interface (SIO2) 15.1 Configuration ..........177 15.2 Control .
Page 120 17.2 Register configuration ..........212 17.3 Function.
Page 121 20.6.4 Flash Memory SUM Output Mode (Operation Command: 90H) ............248 20.6.5 Product ID Code Output Mode (Operation Command: C0H).............. 249 20.6.6 Flash Memory Status Output Mode (Operation Command: C3H) ............251 20.6.7 Flash Memory security program Setting Mode (Operation Command: FAH) ........252 20.7 Error Code .
Page 122 viii...
Page 123: Features
T5CL8 CMOS 8-Bit Microcontroller T5CL8 The T5CL8 is a single-chip 8-bit high-speed and high-functionality microcomputer incorporating 61440 bytes of Flash Memory. Product No. Package MaskROM MCU Emulation Chip (FLASH) 61440 2048 T5CL8 LQFP64-P-1010-0.50D bytes bytes 1.1 Features 1. 8-bit single chip microcomputer TLCS-870/C series - Instruction execution time : 0.25 µs (at 16 MHz) 122 µs (at 32.768 kHz)
Page 124 1.1 Features T5CL8 8. 8-bit timer counter : 4 ch - Timer, Event counter, Programmable divider output (PDO), Pulse width modulation (PWM) output, Programmable pulse generation (PPG) modes 9. 8-bit UART : 2 ch 10. High-Speed SIO: 2ch 11. Serial Bus Interface(I C Bus): 1ch 12.
Page 125: Pin Assignment
T5CL8 1.2 Pin Assignment (INT3/TC2) P15 P74(AIN12) /TC5) P16 PDO5/PWM5 P73(AIN11) /TC6) P17 PDO6/PWM6/PPG6 P72(AIN10) (SCL) P50 P71(AIN9) (SDA) P51 P70(AIN8) P67(AIN7/STOP3) P66(AIN6/STOP2) P65(AIN5/STOP1) P64(AIN4/STOP0) P63(AIN3) P62(AIN2) P61(AIN1) P60(AIN0) AVDD VAREF P07(INT2) Figure 1-1 Pin Assignment Page 3...
Page 126: Block Diagram
1.3 Block Diagram T5CL8 1.3 Block Diagram Figure 1-2 Block Diagram Page 4...
Page 127: Pin Names And Functions
T5CL8 1.4 Pin Names and Functions The T5CL8 has MCU mode, parallel PROM mode, and serial PROM mode. Table 1-1 shows the pin functions in MCU mode. The serial PROM mode is explained later in a separate chapter. Table 1-1 Pin Names and Functions(1/3) Pin Name Pin Number Input/Output...
Page 128 1.4 Pin Names and Functions T5CL8 Table 1-1 Pin Names and Functions(2/3) Pin Name Pin Number Input/Output Functions PORT20 External interrupt 5 input INT5 STOP mode release signal input STOP PORT37 PORT36 PORT35 PORT34 PORT33 PORT32 PORT31 PORT30 PORT47 PORT46 Serial clock input/output 2 SCK2 PORT45...
Page 129 T5CL8 Table 1-1 Pin Names and Functions(3/3) Pin Name Pin Number Input/Output Functions PORT63 AIN3 Analog Input3 PORT62 AIN2 Analog Input2 PORT61 AIN1 Analog Input1 PORT60 AIN0 Analog Input0 PORT77 AIN15 Analog Input15 PORT76 AIN14 Analog Input14 PORT75 AIN13 Analog Input13 PORT74 AIN12 Analog Input12...
Page 130 1.4 Pin Names and Functions T5CL8 Page 8...
Page 131: Operational Description
T5CL8 2. Operational Description 2.1 CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit. 2.1.1 Memory Address Map The T5CL8 memory is composed Flash, RAM, DBR(Data buffer register) and SFR(Special func- tion register).
Page 132: System Clock Controller
2. Operational Description 2.2 System Clock Controller T5CL8 The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Example :Clears RAM to “00H”. (T5CL8) HL, 0040H ;...
Page 133 T5CL8 Low-frequency clock High-frequency clock XOUT XOUT XTIN XTIN XTOUT XTOUT (Open) (Open) (c) Crystal (d) External oscillator (a) Crystal/Ceramic (b) External oscillator resonator Figure 2-3 Examples of Resonator Connection Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with dis- abling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program.
Page 134: Timing Generator
2. Operational Description 2.2 System Clock Controller T5CL8 2.2.2 Timing Generator The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. 1.
Page 135: Machine Cycle
T5CL8 Timing Generator Control Register TBTCR (0036H) (DVOEN) (DVOCK) DV7CK (TBTEN) (TBTCK) (Initial value: 0000 0000) Selection of input to the 7th stage 0: fc/2 [Hz] DV7CK of the divider 1: fs Note 1: In single clock mode, do not set DV7CK to “1”. Note 2: Do not set “1”...
Page 136 2. Operational Description 2.2 System Clock Controller T5CL8 IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (Operate using the high-frequency clock). IDLE1 mode is started by SYSCR2<IDLE> = "1", and IDLE1 mode is released to NORMAL1 mode by an interrupt request from the on-chip peripherals or external interrupt inputs.
Page 137: Stop Mode
T5CL8 Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2<XEN>. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. IDLE2 mode In this mode, the internal oscillation circuit remain active.
Page 138 2. Operational Description 2.2 System Clock Controller T5CL8 IDLE0 RESET Reset release mode Note 2 SYSCR2<TGHALT> = "1" SYSCR2<IDLE> = "1" SYSCR1<STOP> = "1" IDLE1 NORMAL1 mode mode Interrupt STOP pin input (a) Single-clock mode SYSCR2<XTEN> = "0" SYSCR2<XTEN> = "1" SYSCR2<IDLE>...
Page 139 T5CL8 System Control Register 1 SYSCR1 (0038H) STOP RELM RETM OUTEN (Initial value: 0000 00**) 0: CPU core and peripherals remain active STOP STOP mode start 1: CPU core and peripherals are halted (Start STOP mode) Release method for STOP 0: Edge-sensitive release RELM mode...
Page 140: Operating Mode Control
2. Operational Description 2.2 System Clock Controller T5CL8 2.2.4 Operating Mode Control 2.2.4.1 STOP mode STOP mode is controlled by the system control register 1, the pin input and key-on wakeup input STOP (STOP3 to STOP0) which is controlled by the STOP mode release control register (STOPCR). pin is also used both as a port P20 and an (external interrupt input 5) pin.
Page 141 T5CL8 Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST (P2PRD). 0 ; To reject noise, STOP mode does not start if F, SINT5 port P20 is at high (SYSCR1), 01010000B ; Sets up the level-sensitive release mode. ;...
Page 142 2. Operational Description 2.2 System Clock Controller T5CL8 STOP mode is released by the following sequence. 1. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and low- frequency clock oscillators are turned on; when returning to SLOW1 mode, only the low- frequency clock oscillator is turned on.
Page 143 T5CL8 Figure 2-9 STOP Mode Start/Release Page 21...
Page 144: Idle1/2 Mode And Sleep1/2 Mode
2. Operational Description 2.2 System Clock Controller T5CL8 2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. 1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to operate.
Page 145 T5CL8 • Start the IDLE1/2 and SLEEP1/2 modes After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2 and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2<IDLE> to “1”. • Release the IDLE1/2 and SLEEP1/2 modes IDLE1/2 and SLEEP1/2 modes include a normal release mode and an interrupt release mode.
Page 146 2. Operational Description 2.2 System Clock Controller T5CL8 Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release Page 24...
Page 147: Idle0 And Sleep0 Modes (Idle0, Sleep0)
T5CL8 2.2.4.3 IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. 1. Timing generator stops feeding clock to peripherals except TBT. 2.
Page 148 2. Operational Description 2.2 System Clock Controller T5CL8 • Start the IDLE0 and SLEEP0 modes Stop (Disable) peripherals such as a timer counter. To start IDLE0 and SLEEP0 modes, set SYSCR2<TGHALT> to “1”. • Release the IDLE0 and SLEEP0 modes IDLE0 and SLEEP0 modes include a normal release mode and an interrupt release mode.
Page 149 T5CL8 Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release Page 27...
Page 150 2. Operational Description 2.2 System Clock Controller T5CL8 2.2.4.4 SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter. Switching from NORMAL2 mode to SLOW1 mode First, set SYSCR2<SYSCK>...
Page 151 T5CL8 Switching from SLOW1 mode to NORMAL2 mode First, set SYSCR2<XEN> to turn on the high-frequency oscillation. When time for stabilization (Warm up) has been taken by the timer/counter (TC6,TC5), clear SYSCR2<SYSCK> to switch the main system clock to the high-frequency clock. SLOW mode can also be released by inputting low level on the pin.
Page 152 2. Operational Description 2.2 System Clock Controller T5CL8 Figure 2-14 Switching between the NORMAL2 and SLOW Modes Page 30...
Page 153: Reset Circuit
T5CL8 2.3 Reset Circuit The T5CL8 has four types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction reset.
Page 154: Address Trap Reset
2. Operational Description 2.3 Reset Circuit T5CL8 2.3.2 Address trap reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1<ATAS> is set to “1”), DBR or the SFR area, address trap reset will be generated.
Page 155 T5CL8 Page 33...
Page 156 2. Operational Description 2.3 Reset Circuit T5CL8 Page 34...
Page 157: Interrupt Control Circuit
T5CL8 3. Interrupt Control Circuit The T5CL8 has a total of 24 interrupt sources excluding reset. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors. The interrupt latch is set to “1”...
Page 158: Interrupt Enable Register (Eir)
3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) T5CL8 The interrupt latches are located on address 002EH, 003CH and 003DH in SFR area. Each latch can be cleared to "0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the interrupt latch, load instruction should be used and then IL2 and IL3 should be set to "1".
Page 159: Individual Interrupt Enable Flags (Ef23 To Ef4)
T5CL8 3.2.2 Individual interrupt enable flags (EF23 to EF4) Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding bit of an individual interrupt enable flag to “1” enables acceptance of its interrupt, and setting the bit to “0” dis- ables acceptance.
Page 160: Note 3
3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) T5CL8 Interrupt Latches (Initial value: 00000000 000000**) ILH,ILL (003DH, 003CH) IL15 IL14 IL13 IL12 IL11 IL10 ILH (003DH) ILL (003CH) (Initial value: 00000000) (002EH) IL23 IL22 IL21 IL20 IL19 IL18 IL17 IL16 ILE (002EH) at RD...
Page 161: Interrupt Sequence
T5CL8 3.3 Interrupt Sequence An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to “0” by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 µs @16 MHz) after the completion of the current instruction.
Page 162: Saving/Restoring General-Purpose Registers
3. Interrupt Control Circuit 3.3 Interrupt Sequence T5CL8 A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable interrupt higher than the level of current servicing interrupt is requested. In order to utilize nested interrupt service, the IMF is set to “1” in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
Page 163: Interrupt Return
T5CL8 Example :Save/store register using data transfer instructions PINTxx: (GSAVA), A ; Save A register (interrupt processing) A, (GSAVA) ; Restore A register RETI ; RETURN Main task Interrupt Interrupt service task acceptance Saving registers Restoring registers Interrupt return Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing 3.3.3 Interrupt return Interrupt return instructions [RETI]/[RETN] perform as follows.
Page 164: Software Interrupt (Intsw)
3. Interrupt Control Circuit 3.4 Software Interrupt (INTSW) T5CL8 Example 2 :Restarting without returning interrupt (In this case, PSW (Includes IMF) before interrupt acceptance is discarded.) PINTxx: ; Recover SP by 3 (interrupt processing) EIRL, data ; Set IMF to “1” or clear it to “0” Restart Address ;...
Page 165: External Interrupts
T5CL8 3.7 External Interrupts The T5CL8 has 5 external interrupt inputs. These inputs are equipped with digital noise reject circuits (Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1 to INT3. The /P00 pin can be configured as either an external inter- INT0 rupt input pin or an input/output port, and is configured as an input port during reset.
Page 166 3. Interrupt Control Circuit 3.7 External Interrupts T5CL8 External Interrupt Control Register EINTCR (0037H) INT1NC INT0EN INT3ES INT2ES INT1ES (Initial value: 00** 000*) 0: Pulses of less than 63/fc [s] are eliminated as noise INT1NC Noise reject time select 1: Pulses of less than 15/fc [s] are eliminated as noise 0: P00 input/output port INT0EN P00/...
Page 167: Special Function Register (Sfr)
T5CL8 4. Special Function Register (SFR) The T5CL8 adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address 0000H to 003FH, DBR is mapped on address 0F80H to 0FFFH.
Page 168 4. Special Function Register (SFR) 4.1 SFR T5CL8 Address Read Write 0026H TC1CR 0027H TC3CR 0028H TC4CR 0029H TC5CR 002AH TC6CR 002BH SIO2RDB SIO2TDB 002CH EIRE 002DH Reserved 002EH 002FH Reserved 0030H Reserved 0031H SIO2CR 0032H SIO2SR 0033H Reserved 0034H WDTCR1 0035H WDTCR2...
Page 169: Dbr
T5CL8 4.2 DBR Address Read Write 0F80H Reserved 0F81H Reserved 0F82H Reserved 0F83H Reserved 0F84H Reserved 0F85H Reserved 0F86H Reserved 0F87H Reserved 0F88H Reserved 0F89H Reserved 0F8AH Reserved 0F8BH Reserved 0F8CH Reserved 0F8DH Reserved 0F8EH Reserved 0F8FH Reserved 0F90H SBISRA SBICRA 0F91H SBIDBR...
Page 170 4. Special Function Register (SFR) 4.2 DBR T5CL8 Address Read Write 0FE0H Reserved 0FE1H Reserved 0FE2H Reserved 0FE3H Reserved 0FE4H Reserved 0FE5H Reserved 0FE6H Reserved 0FE7H Reserved 0FE8H Reserved 0FE9H Reserved 0FEAH Reserved 0FEBH Reserved 0FECH Reserved 0FEDH Reserved 0FEEH Reserved 0FEFH Reserved...
Page 171: I/O Ports
T5CL8 5. I/O Ports The T5CL8 has 8 parallel input/output ports (56 pins) as follows. Primary Function Secondary Functions External interrupt, Serial PROM mode cotrol input, serial interface input/output, Port P0 8-bit I/O port UART input/output. Port P1 8-bit I/O port External interrupt, timer counter input/output, divider output.
Page 172: Port P0 (P07 To P00)
5. I/O Ports 5.1 Port P0 (P07 to P00) T5CL8 5.1 Port P0 (P07 to P00) Port P0 is an 8-bit input/output port. Port P0 is also used as an external interrupt input, Serial PROM mode control input, a serial interface input/output and an UART input/output.
Page 173 T5CL8 P0DR (0000H) INT2 INT1 TXD1 RXD1 (Initial value: 1111 1111) SCK1 INT0 BOOT (Initial value: 0000 0000) P0OUTCR (0008H) 0: Sink open-drain output P0OUTCR Port P0 output circuit control (Set for each bit individually) 1: C-MOS output P0PRD (000BH) Read only Page 51...
Page 174: Port P1 (P17 To P10)
5. I/O Ports 5.2 Port P1 (P17 to P10) T5CL8 5.2 Port P1 (P17 to P10) Port P1 is an 8-bit input/output port which can be configured as an input or output in one-bit unit. Port P1 is also used as a timer/counter input/output, an external interrupt input and a divider output. Input/output mode is specified by the P1 control register (P1CR).
Page 175 T5CL8 P1DR (0001H) INT3 (Initial value: 0000 0000) PWM6 PWM5 PWM4 PWM3 PDO6 PDO5 PDO4 PDO3 PPG6 PPG4 P1CR (0009H) (Initial value: 0000 0000) 0: Input mode P1CR I/O control for port P1 (Specified for each bit) 1: Output mode Page 53...
Page 176: Port P2 (P22 To P20)
5. I/O Ports 5.3 Port P2 (P22 to P20) T5CL8 5.3 Port P2 (P22 to P20) Port P2 is a 3-bit input/output port. It is also used as an external interrupt, a STOP mode release signal input, and low-frequency crystal oscillator con- nection pins.
Page 177: Port P3 (P37 To P30) (Large Current Port)
T5CL8 5.4 Port P3 (P37 to P30) (Large Current Port) Port P3 is an 8-bit input/output port. When used as an input port, the corresponding output latch (P3DR) should be set to "1". During reset, the P3DR is initialized to "1". P3 port output latch (P3DR) and P3 port terminal input (P3PRD) are located on their respective address.
Page 178: Port P4 (P47 To P40)
5. I/O Ports 5.5 Port P4 (P47 to P40) T5CL8 5.5 Port P4 (P47 to P40) Port P4 is an 8-bit input/output port. Port P4 is also used as a serial interface input/output and an UART input/output. When used as an input port, a serial interface input/output and an UART input/output, the corresponding output latch (P4DR) should be set to "1".
Page 179 T5CL8 P4DR (0004H) (Initial value: 1111 1111) TXD2 RXD2 SCK2 (Initial value: 0000 0000) P4OUTCR (000AH) 0: Sink open-drain output P4OUTCR Port P4 output circuit control (Set for each bit individually) 1: C-MOS output P4PRD (000EH) Read only Page 57...
Page 180: Port P5 (P54 To P50) (Large Current Port)
5. I/O Ports 5.6 Port P5 (P54 to P50) (Large Current Port) T5CL8 5.6 Port P5 (P54 to P50) (Large Current Port) Port P5 is an 5-bit input/output port. Port P5 is also used as an I C Bus input/output. When used as an input port and I C Bus input/output, the corresponding output latch (P5DR) should be set to "1".
Page 181: Port P6 (P67 To P60)
T5CL8 5.7 Port P6 (P67 to P60) Port P6 is an 8-bit input/output port which can be configured as an input or output in one-bit unit. Port P6 is also used as an analog input and key-on wakeup input. Input/output mode is specified by the P6 control register (P6CR1) and P6 input control register (P6CR2). During reset, the P6CR1 is initialized to "0"...
Page 182 5. I/O Ports 5.7 Port P6 (P67 to P60) T5CL8 P6CR2i P6CR2i input P6CR1i P6CR1i input Control input Data input (P6DRi) Data output (P6DRi) STOP OUTTEN Analog input AINDS SAIN a) P63 to P60 Key-on wakeup STOPkEN P6CR2j P6CR2j input P6CR1j P6CR1j input Data input (P6DRj)
Page 183 T5CL8 P6DR (0006H) AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 (Initial value: 0000 0000) STOP3 STOP2 STOP1 STOP0 P6CR1 (0F9BH) (Initial value: 0000 0000) 0: Input mode P6CR1 I/O control for port P6 (Specified for each bit) 1: Output mode P6CR2 (0F9CH) (Initial value: 1111 1111)
Page 184: Port P7 (P77 To P70)
5. I/O Ports 5.8 Port P7 (P77 to P70) T5CL8 5.8 Port P7 (P77 to P70) Port P7 is an 8-bit input/output port which can be configured as an input or output in one-bit unit. Port P7 is also used as an analog input. Input/output mode is specified by the P7 control register (P7CR1) and P7 input control register (P7CR2).
Page 185 T5CL8 P7CR2i P7CR2i input P7CR1i P7CR1i input Control input Data input (P7DRi) Data output (P7DRi) STOP OUTTEN Analog input AINDS SAIN Note 1: i = 7 to 0 Note 2: STOP is bit7 in SYSCR1. Note 3: SAIN is AD input select signal. Figure 5-9 Port 7, P7CR1 and P7CR2 P7DR (0007H)
Page 186 5. I/O Ports 5.8 Port P7 (P77 to P70) T5CL8 Page 64...
Page 187: Watchdog Timer (Wdt)
T5CL8 6. Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the CPU to a system recovery routine. The watchdog timer signal for detecting malfunctions can be programmed only once as “reset request”...
Page 188: Watchdog Timer Control
6. Watchdog Timer (WDT) 6.2 Watchdog Timer Control T5CL8 6.2 Watchdog Timer Control The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watch- dog timer is automatically enabled after the reset release. 6.2.1 Malfunction Detection Methods Using the Watchdog Timer The CPU malfunction is detected, as shown below.
Page 189: Watchdog Timer Enable
T5CL8 Watchdog Timer Control Register 1 WDTCR1 (0034H) (ATAS) (ATOUT) WDTEN WDTT WDTOUT (Initial value: **11 1001) 0: Disable (Writing the disable code to WDTCR2 is required.) Write WDTEN Watchdog timer enable/disable 1: Enable only NORMAL1/2 mode SLOW1/2 mode DV7CK = 0 DV7CK = 1 Watchdog timer detection time Write...
Page 190: Watchdog Timer Disable
6. Watchdog Timer (WDT) 6.2 Watchdog Timer Control T5CL8 6.2.3 Watchdog Timer Disable To disable the watchdog timer, set the register in accordance with the following procedures. Setting the reg- ister in other procedures causes a malfunction of the microcontroller. 1.
Page 191: Watchdog Timer Reset
T5CL8 6.2.5 Watchdog Timer Reset When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, a watchdog timer reset request is generated. When a watchdog timer reset request is generated, the internal hardware is reset. The reset time is maximum 24/fc [s] (1.5 µs @ fc = 16.0 MHz). Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-fre- quency clock) since the high-frequency clock oscillator is restarted.
Page 192: Address Trap
6. Watchdog Timer (WDT) 6.3 Address Trap T5CL8 6.3 Address Trap The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address traps. Watchdog Timer Control Register 1 WDTCR1 (0034H) ATAS ATOUT (WDTEN) (WDTT) (WDTOUT) (Initial value: **11 1001)
Page 193: Address Trap Reset
T5CL8 6.3.4 Address Trap Reset While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the SFR area, address trap reset will be generated.
Page 194 6. Watchdog Timer (WDT) 6.3 Address Trap T5CL8 Page 72...
Page 195: Time Base Timer (Tbt)
T5CL8 7. Time Base Timer (TBT) The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). 7.1 Time Base Timer 7.1.1 Configuration fc/2 or fs/2 fc/2 or fs/2 fc/2 or fs/2 Source clock...
Page 196: Function
7. Time Base Timer (TBT) 7.1 Time Base Timer T5CL8 Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt fre- quency must not be changed with the disable from the enable state.) Both frequency selection and enabling can be per- formed simultaneously.
Page 197: Divider Output (Dvo)
T5CL8 7.2 Divider Output ( Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from pin. 7.2.1 Configuration Output latch Data output DVO pin fc/2 or fs/2 fc/2 or fs/2 fc/2...
Page 198 7. Time Base Timer (TBT) 7.2 Divider Output (DVO) T5CL8 Example :1.95 kHz pulse output (fc = 16.0 MHz) ; DVOCK ← "00" (TBTCR) , 00000000B ; DVOEN ← "1" (TBTCR) , 10000000B Table 7-2 Divider Output Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) Divider Output Frequency [Hz] DVOCK NORMAL1/2, IDLE1/2 Mode...
Page 199: Bit Timercounter 1 (Tc1)
T5CL8 8. 16-Bit TimerCounter 1 (TC1) 8.1 Configuration Figure 8-1 TimerCounter 1 (TC1) Page 77...
Page 200: Timercounter Control
8. 16-Bit TimerCounter 1 (TC1) 8.2 TimerCounter Control T5CL8 8.2 TimerCounter Control The TimerCounter 1 is controlled by the TimerCounter 1 control register (TC1CR) and two 16-bit timer registers (TC1DRA and TC1DRB). Timer Register TC1DRAH (0011H) TC1DRAL (0010H) TC1DRA (0011H, 0010H) (Initial value: 1111 1111 1111 1111) Read/Write TC1DRBH (0013H)
Page 201 T5CL8 Note 4: Auto-capture can be used only in the timer, event counter, and window modes. Note 5: To set the timer registers, the following relationship must be satisfied. TC1DRA > TC1DRB > 1 (PPG output mode), TC1DRA > 1 (other modes) Note 6: Set TFF1 to “0”...
Page 202: Function
8. 16-Bit TimerCounter 1 (TC1) 8.3 Function T5CL8 8.3 Function TimerCounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 8.3.1 Timer mode In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register 1A (TC1DRA) value is detected, an INTTC1 interrupt is generated and the up-counter is cleared.
Page 203 T5CL8 Timer start Source clock Counter n − 1 TC1DRA Match detect Counter clear INTTC1 interruput request Timer mode Source clock Counter m − 2 m − 1 m + 1 m + 2 n − 1 n + 1 Capture Capture TC1DRB...
Page 204: External Trigger Timer Mode
8. 16-Bit TimerCounter 1 (TC1) 8.3 Function T5CL8 8.3.2 External Trigger Timer Mode In the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. For the trigger edge used to start counting, either the rising or falling edge is defined in TC1CR<TC1S>.
Page 205 T5CL8 At the rising edge (TC1S = 10) Count start Count start TC1 pin input Source clock Up-counter n − 1 TC1DRA Match detect Count clear INTTC1 interrupt request Trigger start (METT1 = 0) At the rising Count clear Count start Count start edge (TC1S = 10) TC1 pin input...
Page 206: Event Counter Mode
8. 16-Bit TimerCounter 1 (TC1) 8.3 Function T5CL8 8.3.3 Event Counter Mode In the event counter mode, the up-counter counts up at the edge of the input pulse to the TC1 pin. Either the rising or falling edge of the input pulse is selected as the count up edge in TC1CR<TC1S>. When a match between the up-counter and the TC1DRA value is detected, an INTTC1 interrupt is generated and the up-counter is cleared.
Page 207: Window Mode
T5CL8 8.3.4 Window Mode In the window mode, the up-counter counts up at the rising edge of the pulse that is logical ANDed product of the input pulse to the TC1 pin (window pulse) and the internal source clock. Either the positive logic (count up during high-going pulse) or negative logic (count up during low-going pulse) can be selected.
Page 208: Pulse Width Measurement Mode
8. 16-Bit TimerCounter 1 (TC1) 8.3 Function T5CL8 8.3.5 Pulse Width Measurement Mode In the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. Either the rising or falling edge of the internal clock is selected as the trigger edge in TC1CR<TC1S>.
Page 209 T5CL8 Example :Duty measurement (resolution fc/2 [Hz]) (INTTC1SW). 0 ; INTTC1 service switch initial setting Address set to convert INTTC1SW at each INTTC1 (TC1CR), 00000110B ; Sets the TC1 mode and source clock ; IMF= “0” (EIRL). 5 ; Enables INTTC1 ;...
Page 210 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function T5CL8 Count start Count start TC1 pin input Trigger (TC1S = "10") Internal clock Counter n - 1 Capture TC1DRB INTTC1 interrupt request [Application] High-or low-level pulse width measurement (a) Single-edge capture (MCAP1 = "1") Count start Count start TC1 pin input...
Page 211: Programmable Pulse Generate (Ppg) Output Mode
T5CL8 8.3.6 Programmable Pulse Generate (PPG) Output Mode In the programmable pulse generation (PPG) mode, an arbitrary duty pulse is generated by counting per- formed in the internal clock. To start the timer, TC1CR<TC1S> specifies either the edge of the input pulse to the TC1 pin or the command start.
Page 212 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function T5CL8 Example :Generating a pulse which is high-going for 800 µs and low-going for 200 µs (fc = 16 MHz) Setting port (TC1CR), 10000111B ; Sets the PPG mode, selects the source clock (TC1DRA), 007DH ;...
Page 213 T5CL8 Timer start Internal clock Counter n + 1 n + 1 TC1DRB Match detect TC1DRA PPG pin output INTTC1 interrupt request Note: m > n Continuous pulse generation (TC1S = 01) Count start TC1 pin input Trigger Internal clock Counter n + 1 TC1DRB...
Page 214 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function T5CL8 Page 92...
Page 215: Bit Timer/Counter2 (Tc2)
T5CL8 9. 16-Bit Timer/Counter2 (TC2) 9.1 Configuration TC2S Port (Note) TC2 pin Window Clear fc/2 fs/2 fc/2 fs/2 16-bit up counter Timer/ fc/2 event counter Source clock fc/2 INTTC2 TC2M interrupt Match TC2S TC2CK TC2CR TC2DR TC2 control register 16-bit timer register 2 Note: When control input/output is used, I/O port setting should be set correctly.
Page 216: Control
9. 16-Bit Timer/Counter2 (TC2) 9.2 Control T5CL8 9.2 Control The timer/counter 2 is controlled by a timer/counter 2 control register (TC2CR) and a 16-bit timer register 2 (TC2DR). TC2DR (0025H, TC2DRH (0025H) TC2DRL (0024H) 0024H) (Initial value: 1111 1111 1111 1111) TC2CR (0023H) TC2S...
Page 217: Function
T5CL8 9.3 Function The timer/counter 2 has three operating modes: timer, event counter and window modes. And if fc or fs is selected as the source clock in timer mode, when switching the timer mode from SLOW1 to NORMAL2, the timer/counter2 can generate warm-up time until the oscillator is stable. 9.3.1 Timer mode In this mode, the internal clock is used for counting up.
Page 218 9. 16-Bit Timer/Counter2 (TC2) 9.3 Function T5CL8 Timer start Source clock Up-counter Match detect Counter clear TC2DR INTTC2 interrupt Figure 9-2 Timer Mode Timing Chart Page 96...
Page 219: Event Counter Mode
T5CL8 9.3.2 Event counter mode In this mode, events are counted on the rising edge of the TC2 pin input. The contents of TC2DR are com- pared with the contents of the up counter. If a match is found, an INTTC2 interrupt is generated, and the counter is cleared.
Page 220 9. 16-Bit Timer/Counter2 (TC2) 9.3 Function T5CL8 Example :Generates an interrupt, inputting “H” level pulse width of 120 ms or more. (at fc = 16 MHz, TBTCR<DV7CK> = “0” ) (TC2DR), 00EAH ; Sets TC2DR (120 ms ³ /fc = 00EAH) ;...
Page 221: Bit Timercounter (Tc3, Tc4)
T5CL8 10. 8-Bit TimerCounter (TC3, TC4) 10.1 Configuration PWM mode Overflow INTTC4 interrupt request fc/2 or fs/2 Clear 8-bit up-counter fc/2 fc/2 TC4S fc/2 PDO, PPG mode Toggle fc/2 16-bit mode TC4 pin PDO4/PWM4/ 16-bit mode PPG4 pin Clear TC4M Timer F/F4 TC4S TC4CK...
Page 222: Timercounter Control
10. 8-Bit TimerCounter (TC3, TC4) 10.1 Configuration T5CL8 10.2 TimerCounter Control The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers (TTREG3, PWREG3). TimerCounter 3 Timer Register TTREG3 (0014H) (Initial value: 1111 1111) PWREG3 (0018H) (Initial value: 1111 1111)
Page 223 T5CL8 Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 10- Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the high-frequency warm-up mode. Page 101...
Page 224 10. 8-Bit TimerCounter (TC3, TC4) 10.1 Configuration T5CL8 The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and two 8-bit timer registers (TTREG4 and PWREG4). TimerCounter 4 Timer Register TTREG4 (0015H) (Initial value: 1111 1111) PWREG4 (0019H) (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG4) setting while the timer is running.
Page 225 T5CL8 Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC3CR<TC3CK>. Set the timer start control and timer F/F control by programming TC4S and TFF4, respectively. Note 7: The operating clock settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 10-1 and Table 10-2.
Page 226 10. 8-Bit TimerCounter (TC3, TC4) 10.1 Configuration T5CL8 Table 10-3 Constraints on Register Values Being Compared Operating mode Register Value 8-bit timer/event counter 1≤ (TTREGn) ≤255 1≤ (TTREGn) ≤255 8-bit PDO 2≤ (PWREGn) ≤254 8-bit PWM 1≤ (TTREG4, 3) ≤65535 16-bit timer/event counter 256≤...
Page 227: Function
T5CL8 10.3 Function The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8- bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a 16- bit timer.
Page 228: 8-Bit Event Counter Mode (Tc3, 4)
10. 8-Bit TimerCounter (TC3, TC4) 10.1 Configuration T5CL8 TC4CR<TC4S> Internal Source Clock Counter TTREG4 Match detect Counter clear Counter clear Match detect INTTC4 interrupt request Figure 10-2 8-Bit Timer Mode Timing Chart (TC4) 10.3.2 8-Bit Event Counter Mode (TC3, 4) In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin.
Page 229 T5CL8 Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz) Setting port ÷ ÷ (TTREG4), 3DH : 1/1024 2 = 3DH (TC4CR), 00010001B : Sets the operating clock to fc/2 , and 8-bit PDO mode. (TC4CR), 00011001B : Starts TC4. Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running.
Page 230 10. 8-Bit TimerCounter (TC3, TC4) 10.1 Configuration T5CL8 Figure 10-4 8-Bit PDO Mode Timing Chart (TC4) Page 108...
Page 231: 8-Bit Pulse Width Modulation (Pwm) Output Mode (Tc3, 4)
T5CL8 10.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4) This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The up-counter counts up using the internal clock. When a match between the up-counter and the PWREGj value is detected, the logic level output from the timer F/Fj is switched to the opposite state.
Page 232 10. 8-Bit TimerCounter (TC3, TC4) 10.1 Configuration T5CL8 Figure 10-5 8-Bit PWM Mode Timing Chart (TC4) Page 110...
Page 233: 16-Bit Timer Mode (Tc3 And 4)
T5CL8 10.3.5 16-Bit Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascad- able to form a 16-bit timer. When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the timer is started by setting TC4CR<TC4S>...
Page 234: 16-Bit Event Counter Mode (Tc3 And 4)
10. 8-Bit TimerCounter (TC3, TC4) 10.1 Configuration T5CL8 10.3.6 16-Bit Event Counter Mode (TC3 and 4) In the event counter mode, the up-counter counts up at the falling edge to the TC3 pin. The TimerCounter 3 and 4 are cascadable to form a 16-bit event counter. When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the timer is started by setting TC4CR<TC4S>...
Page 235 T5CL8 CLR (TC4CR).3: Stops the timer. CLR (TC4CR).7 : Sets the 4 pin to the high level. Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered with- out stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the pin during the warm-up period time after exiting the STOP mode.
Page 236 10. 8-Bit TimerCounter (TC3, TC4) 10.1 Configuration T5CL8 Figure 10-7 16-Bit PWM Mode Timing Chart (TC3 and TC4) Page 114...
Page 237: 16-Bit Programmable Pulse Generate (Ppg) Output Mode (Tc3 And 4)
T5CL8 10.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 3 and 4 are cascad- able to enter the 16-bit PPG mode. The counter counts up using the internal clock or external clock.
Page 238 10. 8-Bit TimerCounter (TC3, TC4) 10.1 Configuration T5CL8 Figure 10-8 16-Bit PPG Mode Timing Chart (TC3 and TC4) Page 116...
Page 239: Warm-Up Counter Mode
T5CL8 10.3.9 Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 3 and 4 are cascadable to form a 16-bit TimerCounter.
Page 240: High-Frequency Warm-Up Counter Mode (Slow1 → Slow2 → Normal2 → Normal1)
10. 8-Bit TimerCounter (TC3, TC4) 10.1 Configuration T5CL8 10.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 → SLOW2 → NORMAL2 → NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta- bility is obtained. Before starting the timer, set SYSCR2<XEN> to 1 to oscillate the high-frequency clock. When a match between the up-counter and the timer register (TTREG4, 3) value is detected after the timer is started by setting TC4CR<TC4S>...
Page 241: Bit Timercounter (Tc5, Tc6)
T5CL8 11. 8-Bit TimerCounter (TC5, TC6) 11.1 Configuration PWM mode Overflow INTTC6 interrupt request fc/2 or fs/2 Clear 8-bit up-counter fc/2 fc/2 TC6S fc/2 PDO, PPG mode Toggle fc/2 16-bit mode TC6 pin PDO6/PWM6/ 16-bit mode PPG6 pin Clear TC6M Timer F/F6 TC6S TC6CK...
Page 242: Timercounter Control
11. 8-Bit TimerCounter (TC5, TC6) 11.1 Configuration T5CL8 11.2 TimerCounter Control The TimerCounter 5 is controlled by the TimerCounter 5 control register (TC5CR) and two 8-bit timer registers (TTREG5, PWREG5). TimerCounter 5 Timer Register TTREG5 (0016H) (Initial value: 1111 1111) PWREG5 (001AH) (Initial value: 1111 1111)
Page 243 T5CL8 Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 11- Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the high-frequency warm-up mode. Page 121...
Page 244 11. 8-Bit TimerCounter (TC5, TC6) 11.1 Configuration T5CL8 The TimerCounter 6 is controlled by the TimerCounter 6 control register (TC6CR) and two 8-bit timer registers (TTREG6 and PWREG6). TimerCounter 6 Timer Register TTREG6 (0017H) (Initial value: 1111 1111) PWREG6 (001BH) (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG6) setting while the timer is running.
Page 245 T5CL8 Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC5CR<TC5CK>. Set the timer start control and timer F/F control by programming TC6S and TFF6, respectively. Note 7: The operating clock settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 11-1 and Table 11-2.
Page 246 11. 8-Bit TimerCounter (TC5, TC6) 11.1 Configuration T5CL8 Table 11-3 Constraints on Register Values Being Compared Operating mode Register Value 8-bit timer/event counter 1≤ (TTREGn) ≤255 1≤ (TTREGn) ≤255 8-bit PDO 2≤ (PWREGn) ≤254 8-bit PWM 1≤ (TTREG6, 5) ≤65535 16-bit timer/event counter 256≤...
Page 247: Function
T5CL8 11.3 Function The TimerCounter 5 and 6 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8- bit pulse width modulation (PWM) output modes. The TimerCounter 5 and 6 (TC5, 6) are cascadable to form a 16- bit timer.
Page 248: 8-Bit Event Counter Mode (Tc5, 6)
11. 8-Bit TimerCounter (TC5, TC6) 11.1 Configuration T5CL8 TC6CR<TC6S> Internal Source Clock Counter TTREG6 Match detect Counter clear Counter clear Match detect INTTC6 interrupt request Figure 11-2 8-Bit Timer Mode Timing Chart (TC6) 11.3.2 8-Bit Event Counter Mode (TC5, 6) In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin.
Page 249 T5CL8 Example :Generating 1024 Hz pulse using TC6 (fc = 16.0 MHz) Setting port ÷ ÷ (TTREG6), 3DH : 1/1024 2 = 3DH (TC6CR), 00010001B : Sets the operating clock to fc/2 , and 8-bit PDO mode. (TC6CR), 00011001B : Starts TC6. Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running.
Page 250 11. 8-Bit TimerCounter (TC5, TC6) 11.1 Configuration T5CL8 Figure 11-4 8-Bit PDO Mode Timing Chart (TC6) Page 128...
Page 251: 8-Bit Pulse Width Modulation (Pwm) Output Mode (Tc5, 6)
T5CL8 11.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC5, 6) This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The up-counter counts up using the internal clock. When a match between the up-counter and the PWREGj value is detected, the logic level output from the timer F/Fj is switched to the opposite state.
Page 252 11. 8-Bit TimerCounter (TC5, TC6) 11.1 Configuration T5CL8 Figure 11-5 8-Bit PWM Mode Timing Chart (TC6) Page 130...
Page 253: 16-Bit Timer Mode (Tc5 And 6)
T5CL8 11.3.5 16-Bit Timer Mode (TC5 and 6) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 5 and 6 are cascad- able to form a 16-bit timer. When a match between the up-counter and the timer register (TTREG5, TTREG6) value is detected after the timer is started by setting TC6CR<TC6S>...
Page 254: 16-Bit Event Counter Mode (Tc5 And 6)
11. 8-Bit TimerCounter (TC5, TC6) 11.1 Configuration T5CL8 11.3.6 16-Bit Event Counter Mode (TC5 and 6) In the event counter mode, the up-counter counts up at the falling edge to the TC5 pin. The TimerCounter 5 and 6 are cascadable to form a 16-bit event counter. When a match between the up-counter and the timer register (TTREG5, TTREG6) value is detected after the timer is started by setting TC6CR<TC6S>...
Page 255 T5CL8 CLR (TC6CR).3: Stops the timer. CLR (TC6CR).7 : Sets the 6 pin to the high level. Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered with- out stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the pin during the warm-up period time after exiting the STOP mode.
Page 256 11. 8-Bit TimerCounter (TC5, TC6) 11.1 Configuration T5CL8 Figure 11-7 16-Bit PWM Mode Timing Chart (TC5 and TC6) Page 134...
Page 257: 16-Bit Programmable Pulse Generate (Ppg) Output Mode (Tc5 And 6)
T5CL8 11.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC5 and 6) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 5 and 6 are cascad- able to enter the 16-bit PPG mode. The counter counts up using the internal clock or external clock.
Page 258 11. 8-Bit TimerCounter (TC5, TC6) 11.1 Configuration T5CL8 Figure 11-8 16-Bit PPG Mode Timing Chart (TC5 and TC6) Page 136...
Page 259: Warm-Up Counter Mode
T5CL8 11.3.9 Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 5 and 6 are cascadable to form a 16-bit TimerCounter.
Page 260 11. 8-Bit TimerCounter (TC5, TC6) 11.1 Configuration T5CL8 11.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 → SLOW2 → NORMAL2 → NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta- bility is obtained. Before starting the timer, set SYSCR2<XEN> to 1 to oscillate the high-frequency clock. When a match between the up-counter and the timer register (TTREG6, 5) value is detected after the timer is started by setting TC6CR<TC6S>...
Page 261: Asynchronous Serial Interface (Uart1 )
T5CL8 12. Asynchronous Serial interface (UART1 ) 12.1 Configuration UART control register 1 Transmit data buffer Receive data buffer UART1CR1 TD1BUF RD1BUF Shift register Parity bit Shift register Stop bit INTTXD1 Noise rejection RXD1 circuit TXD1 INTRXD1 Transmit/receive clock fc/2 fc/2 fc/2 fc/13...
Page 262: Control
12. Asynchronous Serial interface (UART1 ) 12.2 Control T5CL8 12.2 Control UART1 is controlled by the UART1 Control Registers (UART1CR1, UART1CR2). The operating status can be monitored using the UART status register (UART1SR). UART1 Control Register1 UART1CR1 (0F95H) STBT EVEN (Initial value: 0000 0000) Disable Transfer operation...
Page 263 T5CL8 UART1 Status Register UART1SR (0F95H) PERR FERR OERR RBFL TEND TBEP (Initial value: 0000 11**) No parity error PERR Parity error flag Parity error No framing error FERR Framing error flag Framing error No overrun error OERR Overrun error flag Overrun error Read only...
Page 264: Transfer Data Format
12. Asynchronous Serial interface (UART1 ) 12.3 Transfer Data Format T5CL8 12.3 Transfer Data Format In UART1, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UART1CR1<STBT>), and parity (Select parity in UART1CR1<PE>; even- or odd-numbered parity by UART1CR1<EVEN>) are added to the transfer data.
Page 265: Transfer Rate
T5CL8 12.4 Transfer Rate The baud rate of UART1 is set of UART1CR1<BRG>. The example of the baud rate are shown as follows. Table 12-1 Transfer Rate (Example) Source Clock 16 MHz 8 MHz 4 MHz 76800 [baud] 38400 [baud] 19200 [baud] 38400 19200...
Page 266: Stop Bit Length
12. Asynchronous Serial interface (UART1 ) 12.6 STOP Bit Length T5CL8 12.6 STOP Bit Length Select a transmit stop bit length (1 bit or 2 bits) by UART1CR1<STBT>. 12.7 Parity Set parity / no parity by UART1CR1<PE> and set parity type (Odd- or Even-numbered) by UART1CR1<EVEN>.
Page 267: Status Flag
T5CL8 12.9 Status Flag 12.9.1 Parity Error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UART1SR<PERR> is set to “1”. The UART1SR<PERR> is cleared to “0” when the RD1BUF is read after reading the UART1SR.
Page 268: Receive Data Buffer Full
12. Asynchronous Serial interface (UART1 ) 12.9 Status Flag T5CL8 UART1SR<RBFL> Stop RXD1 pin Final bit xxx0 ** xxxx0 1xxxx0 Shift register RD1BUF yyyy UART1SR<OERR> After reading UART1SR then RD1BUF clears OERR. INTRXD1 interrupt Figure 12-7 Generation of Overrun Error Note:Receive operations are disabled until the overrun error flag UART1SR<OERR>...
Page 269: Transmit End Flag
T5CL8 Data write Data write zzzz xxxx yyyy TD1BUF ***** 1 1xxxx0 * 1xxxx **** 1x ***** 1 1yyyy0 Shift register Start Bit 0 Final bit Stop TXD1 pin UART1SR<TBEP> After reading UART1SR writing TD1BUF clears TBEP. INTTXD1 interrupt Figure 12-9 Generation of Transmit Data Buffer Empty 12.9.6 Transmit End Flag When data are transmitted and no data is in TD1BUF (UART1SR<TBEP>...
Page 270 12. Asynchronous Serial interface (UART1 ) 12.9 Status Flag T5CL8 Page 148...
Page 271: Asynchronous Serial Interface (Uart2 )
T5CL8 13. Asynchronous Serial interface (UART2 ) 13.1 Configuration UART control register 1 Transmit data buffer Receive data buffer UART2CR1 TD2BUF RD2BUF Shift register Parity bit Shift register Stop bit INTTXD2 Noise rejection RXD2 circuit TXD2 INTRXD2 Transmit/receive clock fc/2 fc/2 fc/2 fc/13...
Page 272: Control
13. Asynchronous Serial interface (UART2 ) 13.2 Control T5CL8 13.2 Control UART2 is controlled by the UART2 Control Registers (UART2CR1, UART2CR2). The operating status can be monitored using the UART status register (UART2SR). UART2 Control Register1 UART2CR1 (0F98H) STBT EVEN (Initial value: 0000 0000) Disable Transfer operation...
Page 273 T5CL8 UART2 Status Register UART2SR (0F98H) PERR FERR OERR RBFL TEND TBEP (Initial value: 0000 11**) No parity error PERR Parity error flag Parity error No framing error FERR Framing error flag Framing error No overrun error OERR Overrun error flag Overrun error Read only...
Page 274: Transfer Data Format
13. Asynchronous Serial interface (UART2 ) 13.3 Transfer Data Format T5CL8 13.3 Transfer Data Format In UART2, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UART2CR1<STBT>), and parity (Select parity in UART2CR1<PE>; even- or odd-numbered parity by UART2CR1<EVEN>) are added to the transfer data.
Page 275: Transfer Rate
T5CL8 13.4 Transfer Rate The baud rate of UART2 is set of UART2CR1<BRG>. The example of the baud rate are shown as follows. Table 13-1 Transfer Rate (Example) Source Clock 16 MHz 8 MHz 4 MHz 76800 [baud] 38400 [baud] 19200 [baud] 38400 19200...
Page 276: Stop Bit Length
13. Asynchronous Serial interface (UART2 ) 13.6 STOP Bit Length T5CL8 13.6 STOP Bit Length Select a transmit stop bit length (1 bit or 2 bits) by UART2CR1<STBT>. 13.7 Parity Set parity / no parity by UART2CR1<PE> and set parity type (Odd- or Even-numbered) by UART2CR1<EVEN>.
Page 277: Status Flag
T5CL8 13.9 Status Flag 13.9.1 Parity Error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UART2SR<PERR> is set to “1”. The UART2SR<PERR> is cleared to “0” when the RD2BUF is read after reading the UART2SR.
Page 278: Receive Data Buffer Full
13. Asynchronous Serial interface (UART2 ) 13.9 Status Flag T5CL8 UART2SR<RBFL> Stop RXD2 pin Final bit xxx0 ** xxxx0 1xxxx0 Shift register RD2BUF yyyy UART2SR<OERR> After reading UART2SR then RD2BUF clears OERR. INTRXD2 interrupt Figure 13-7 Generation of Overrun Error Note:Receive operations are disabled until the overrun error flag UART2SR<OERR>...
Page 279: Transmit End Flag
T5CL8 Data write Data write zzzz xxxx yyyy TD2BUF ***** 1 1xxxx0 * 1xxxx **** 1x ***** 1 1yyyy0 Shift register Start Bit 0 Final bit Stop TXD2 pin UART2SR<TBEP> After reading UART2SR writing TD2BUF clears TBEP. INTTXD2 interrupt Figure 13-9 Generation of Transmit Data Buffer Empty 13.9.6 Transmit End Flag When data are transmitted and no data is in TD2BUF (UART2SR<TBEP>...
Page 280 13. Asynchronous Serial interface (UART2 ) 13.9 Status Flag T5CL8 Page 158...
Page 281: Synchronous Serial Interface (Sio1)
T5CL8 14. Synchronous Serial Interface (SIO1) The serial interfaces connect to an external device via SI1, SO1, and pins. SCK1 When these pins are used as serial interface, the output latches for each port should be set to "1". 14.1 Configuration Internal data bus SIO1SR SIO1CR...
Page 282: Control
14. Synchronous Serial Interface (SIO1) 14.2 Control T5CL8 14.2 Control The SIO is controlled using the serial interface control register (SIO1CR). The operating status of the serial inter- face can be inspected by reading the status register (SIO1CR). Serial Interface Control Register SIO1CR (0020H) SIOS...
Page 283 T5CL8 Serial Interface Status Register SIO1SR (0021H) SIOF TXERR RXERR (Initial value: 0010 00**) Serial transfer operation status 0: Transfer finished SIOF monitor 1: Transfer in progress 0: 8 clocks Number of clocks monitor 1: 1 to 7 clocks Read only 0: Data exists in transmit buffer Transmit buffer empty flag...
Page 284: Function
14. Synchronous Serial Interface (SIO1) 14.3 Function T5CL8 14.3 Function 14.3.1 Serial clock 14.3.1.1 Clock source The serial clock can be selected by using SIO1CR<SCK>. When the serial clock is changed, the writing instruction to SIO1CR<SCK> should be executed while the transfer is stopped (when SIO1SR<SIOF> “0”) Internal clock Setting the SIO1CR<SCK>...
Page 285: Shift Edge
T5CL8 External clock When an external clock is selected by setting SIO1CR<SCK> to “111B”, the clock via the SCK1 pin from an external source is used as the serial clock. To ensure shift operation, the serial clock pulse width must be 4/fc or more for both “H” and “L” levels.
Page 286: Transfer Bit Direction
14. Synchronous Serial Interface (SIO1) 14.3 Function T5CL8 14.3.2 Transfer bit direction Transfer data direction can be selected by using SIO1CR<SIODIR>. The transfer data direction can't be set individually for transmit and receive operations. When the data direction is changed, the writing instruction to SIO1CR<SIODIR> should be executed while the transfer is stopped (when SIO1CR<SIOF>= “0”) SIOCR<SIOS>...
Page 287: Transmit/Receive Mode
T5CL8 LSB receive mode LSB receive mode is selected by setting SIO1CR<SIODIR> to “1”, in which case the data is received sequentially beginning with the least significant bit (Bit0). 14.3.2.3 Transmit/receive mode MSB transmit/receive mode MSB transmit/receive mode are selected by setting SIO1CR<SIODIR> to “0” in which case the data is transferred sequentially beginning with the most significant bit (Bit7) and the data is received sequentially beginning with the most significant (Bit7).
Page 288 14. Synchronous Serial Interface (SIO1) 14.3 Function T5CL8 During the transmit operation When data is written to SIO1TDB, SIO1SR<TXF> is cleared to “0”. In internal clock operation, in case a next transmit data is not written to SIO1TDB, the serial clock stops to “H”...
Page 289 T5CL8 Writing transmit data Clearing SIOS SIO1CR<SIOS> SIO1SR<SIOF> Start shift Start shift Start shift operation operation operation SIO1SR<SEF> SCK1 SO1 pin A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 SIO1SR<TXF>...
Page 290 14. Synchronous Serial Interface (SIO1) 14.3 Function T5CL8 SIO1CR<SIOS> SIO1SR<SIOF> Start shift Start shift Start shift operation operation operation SIO1SR<SEF> SCK1 A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 SO1 pin SIO1SR<TXF> SIO1SR<TXERR>...
Page 291 T5CL8 If received data is not read out from SIO1RDB receive error occurs immediately after shift opera- tion is finished. Then INTSIO1 interrupt request is generated after SIO1SR<RXERR> is set to “1”. Stopping the receive operation There are two ways for stopping the receive operation. •...
Page 292 14. Synchronous Serial Interface (SIO1) 14.3 Function T5CL8 Reading received data Clearing SIOS SIO1CR<SIOS> SIO1SR<SIOF> Start shift Start shift Start shift operation operation operation SIO1SR<SEF> SCK1 SI1 pin A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 SIO1SR<RXF>...
Page 293: Transmit/Receive Mode
T5CL8 SIO1CR<SIOS> SIO1SR<SIOF> Start shift Start shift Start shift operation operation operation SIO1SR<SEF> SCK1 SI1 pin A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 SIO1SR<RXF>...
Page 294 14. Synchronous Serial Interface (SIO1) 14.3 Function T5CL8 During the transmit/receive operation When data is written to SIO1TDB, SIO1SR<TXF> is cleared to “0” and when a data is read from SIO1RDB, SIO1SR<RXF> is cleared to “0”. In internal clock operation, in case of the condition described below, the serial clock stops to “H” level by an automatic-wait function when all of the bit set in the data has been transmitted.
Page 295 T5CL8 Clearing SIOS SIO1CR<SIOS> Start shift Start shift Start shift SIO1SR<SIOF> operation operation operation SIO1SR<SEF> pin output SCK1 Automatic wait Automatic wait SO1 pin A6 A5 A4 A3 A2 A1 B7 B6 B5 B4 B3 B2 B1 C6 C5 C4 C3 C2 C1 C0 D6 D5 D4 D3 D2 D1 E7 E6 E5 E4 E3 E2 E1 F6 F5 F4 F3 F2 F1 F0...
Page 296 14. Synchronous Serial Interface (SIO1) 14.3 Function T5CL8 Reading received data Writing transmit data Clearing SIOS SIO1CR<SIOS> SIO1SR<SIOF> Start shift Start shift Start shift operation operation operation SIO1SR<SEF> pin output SCK1 SO1 pin A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 SI1 pin D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0 INTSIO1...
Page 297 T5CL8 SIO1CR<SIOS> SIO1SR<SIOF> Start shift Start shift Start shift operation operation operation SIO1SR<SEF> pin output SCK1 SO1 pin A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 SI1 pin D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0 INTSIO1 interrupt request...
Page 298 14. Synchronous Serial Interface (SIO1) 14.3 Function T5CL8 SIO1CR<SIOS> SIO1SR<SIOF> Start shift Start shift Start shift operation operation operation SIO1SR<SEF> pin output SCK1 SO1 pin A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 SI1 pin D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0 INTSIO1...
Page 299: Synchronous Serial Interface (Sio2)
T5CL8 15. Synchronous Serial Interface (SIO2) The serial interfaces connect to an external device via SI2, SO2, and pins. SCK2 When these pins are used as serial interface, the output latches for each port should be set to "1". 15.1 Configuration Internal data bus SIO2SR SIO2CR...
Page 300: Control
15. Synchronous Serial Interface (SIO2) 15.2 Control T5CL8 15.2 Control The SIO is controlled using the serial interface control register (SIO2CR). The operating status of the serial inter- face can be inspected by reading the status register (SIO2CR). Serial Interface Control Register SIO2CR (0031H) SIOS...
Page 301 T5CL8 Serial Interface Status Register SIO2SR (0032H) SIOF TXERR RXERR (Initial value: 0010 00**) Serial transfer operation status 0: Transfer finished SIOF monitor 1: Transfer in progress 0: 8 clocks Number of clocks monitor 1: 1 to 7 clocks Read only 0: Data exists in transmit buffer Transmit buffer empty flag...
Page 302: Function
15. Synchronous Serial Interface (SIO2) 15.3 Function T5CL8 15.3 Function 15.3.1 Serial clock 15.3.1.1 Clock source The serial clock can be selected by using SIO2CR<SCK>. When the serial clock is changed, the writing instruction to SIO2CR<SCK> should be executed while the transfer is stopped (when SIO2SR<SIOF> “0”) Internal clock Setting the SIO2CR<SCK>...
Page 303: Shift Edge
T5CL8 External clock When an external clock is selected by setting SIO2CR<SCK> to “111B”, the clock via the SCK2 pin from an external source is used as the serial clock. To ensure shift operation, the serial clock pulse width must be 4/fc or more for both “H” and “L” levels.
Page 304: Transfer Bit Direction
15. Synchronous Serial Interface (SIO2) 15.3 Function T5CL8 15.3.2 Transfer bit direction Transfer data direction can be selected by using SIO2CR<SIODIR>. The transfer data direction can't be set individually for transmit and receive operations. When the data direction is changed, the writing instruction to SIO2CR<SIODIR> should be executed while the transfer is stopped (when SIO2CR<SIOF>= “0”) SIO2CR<SIOS>...
Page 305: Transmit/Receive Mode
T5CL8 LSB receive mode LSB receive mode is selected by setting SIO2CR<SIODIR> to “1”, in which case the data is received sequentially beginning with the least significant bit (Bit0). 15.3.2.3 Transmit/receive mode MSB transmit/receive mode MSB transmit/receive mode are selected by setting SIO2CR<SIODIR> to “0” in which case the data is transferred sequentially beginning with the most significant bit (Bit7) and the data is received sequentially beginning with the most significant (Bit7).
Page 306 15. Synchronous Serial Interface (SIO2) 15.3 Function T5CL8 During the transmit operation When data is written to SIO2TDB, SIO2SR<TXF> is cleared to “0”. In internal clock operation, in case a next transmit data is not written to SIO2TDB, the serial clock stops to “H”...
Page 307 T5CL8 Writing transmit data Clearing SIOS SIO2CR<SIOS> SIO2SR<SIOF> Start shift Start shift Start shift operation operation operation SIO2SR<SEF> SCK2 SO2 pin A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 SIO2SR<TXF>...
Page 308 15. Synchronous Serial Interface (SIO2) 15.3 Function T5CL8 SIO2CR<SIOS> SIO2SR<SIOF> Start shift Start shift Start shift operation operation operation SIO2SR<SEF> SCK2 A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 SO2 pin SIO2SR<TXF> SIO2SR<TXERR>...
Page 309 T5CL8 If received data is not read out from SIO2RDB receive error occurs immediately after shift opera- tion is finished. Then INTSIO2 interrupt request is generated after SIO2SR<RXERR> is set to “1”. Stopping the receive operation There are two ways for stopping the receive operation. •...
Page 310 15. Synchronous Serial Interface (SIO2) 15.3 Function T5CL8 Reading received data Clearing SIOS SIO2CR<SIOS> SIO2SR<SIOF> Start shift Start shift Start shift operation operation operation SIO2SR<SEF> SCK2 SI2 pin A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 SIO2SR<RXF>...
Page 311: Transmit/Receive Mode
T5CL8 SIO2CR<SIOS> SIO2SR<SIOF> Start shift Start shift Start shift operation operation operation SIO2SR<SEF> SCK2 SI2 pin A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 SIO2SR<RXF>...
Page 312 15. Synchronous Serial Interface (SIO2) 15.3 Function T5CL8 During the transmit/receive operation When data is written to SIO2TDB, SIO2SR<TXF> is cleared to “0” and when a data is read from SIO2RDB, SIO2SR<RXF> is cleared to “0”. In internal clock operation, in case of the condition described below, the serial clock stops to “H” level by an automatic-wait function when all of the bit set in the data has been transmitted.
Page 313 T5CL8 Clearing SIOS SIO2CR<SIOS> Start shift Start shift Start shift SIO2SR<SIOF> operation operation operation SIO2SR<SEF> pin output SCK2 Automatic wait Automatic wait SO2 pin A6 A5 A4 A3 A2 A1 B7 B6 B5 B4 B3 B2 B1 C6 C5 C4 C3 C2 C1 C0 D6 D5 D4 D3 D2 D1 E7 E6 E5 E4 E3 E2 E1 F6 F5 F4 F3 F2 F1 F0...
Page 314 15. Synchronous Serial Interface (SIO2) 15.3 Function T5CL8 Reading received data Writing transmit data Clearing SIOS SIO2CR<SIOS> SIO2SR<SIOF> Start shift Start shift Start shift operation operation operation SIO2SR<SEF> pin output SCK2 SO2 pin A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 SI2 pin D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0 INTSIO2...
Page 315 T5CL8 SIO2CR<SIOS> SIO2SR<SIOF> Start shift Start shift Start shift operation operation operation SIO2SR<SEF> pin output SCK2 SO2 pin A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 SI2 pin D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0 INTSIO2 interrupt request...
Page 316 15. Synchronous Serial Interface (SIO2) 15.3 Function T5CL8 SIO2CR<SIOS> SIO2SR<SIOF> Start shift Start shift Start shift operation operation operation SIO2SR<SEF> pin output SCK2 SO2 pin A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 SI2 pin D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0 INTSIO2...
Page 317: Configuration
T5CL8 16. Serial Bus Interface(I C Bus) Ver.-D (SBI) The T5CL8 has a serial bus interface which employs an I C bus. The serial interface is connected to an external devices through SDA and SCL. The serial bus interface pins are also used as the port. When used as serial bus interface pins, set the output latches of these pins to "1".
Page 318: The Data Format In The I2C Bus Mode
16. Serial Bus Interface(I2C Bus) Ver.-D (SBI) 16.4 The Data Format in the I2C Bus Mode T5CL8 16.4 The Data Format in the I C Bus Mode The data format of the I C bus is shown below. (a) Addressing format 8 bits 1 to 8 bits 1 to 8 bits...
Page 319: I2C Bus Control
T5CL8 16.5 I C Bus Control The following registers are used to control the serial bus interface and monitor the operation status of the I C bus. Serial Bus Interface Control Register A SBICRA (0F90H) (Initial value: 0000 *000) ACK = 0 ACK = 1 Number of Number of...
Page 320 16. Serial Bus Interface(I2C Bus) Ver.-D (SBI) 16.5 I2C Bus Control T5CL8 C bus Address Register I2CAR (0F92H) Slave address (Initial value: 0000 0000) Slave address selection Write Slave address recognition Address recognition mode spec- only ification Non slave address recognition Note 1: I2CAR is write-only register, which cannot be used with any of read-modify-write instruction such as bit manipulation, etc.
Page 321: Acknowledgement Mode Specification
T5CL8 Slave Master/slave selection status monitor Master Receiver Transmitter/receiver selection status monitor Transmitter Bus free Bus status monitor Bus busy Requesting interrupt service Interrupt service requests sta- tus monitor Releasing interrupt service request Read only – Arbitration lost detection monitor Arbitration lost detected Slave address match detection monitor...
Page 322: Number Of Transfer Bits
16. Serial Bus Interface(I2C Bus) Ver.-D (SBI) 16.5 I2C Bus Control T5CL8 In the master mode, a clock pulse for an acknowledge signal is not generated. In the slave mode, a clock for a acknowledge signal is not counted. 16.5.2 Number of transfer bits The BC (Bits7 to 5 in SBICRA) is used to select a number of bits for next transmitting and receiving data.
Page 323: Slave Address And Address Recognition Mode Specification
T5CL8 The serial bus interface circuit has a clock synchronization function. This function ensures normal transfer even if there are two or more masters on the same bus. The example explains clock synchronization procedures when two masters simultaneously exist on a bus.
Page 324: Start/Stop Condition Generation
16. Serial Bus Interface(I2C Bus) Ver.-D (SBI) 16.5 I2C Bus Control T5CL8 When a stop condition on the bus or an arbitration lost is detected, the TRX is cleared to “0” by the hardware. " Table 16-2 TRX changing conditions in each mode " shows TRX changing conditions in each mode and TRX value after changing Table 16-2 TRX changing conditions in each mode Mode...
Page 325: Setting Of I2C Bus Mode
T5CL8 In the slave mode, the conditions of generating INTSBI interrupt request are follows: • At the end of acknowledge signal when the received slave address matches to the value set by the I2CAR • At the end of acknowledge signal when a “GENERAL CALL” is received •...
Page 326: Slave Address Match Detection Monitor
16. Serial Bus Interface(I2C Bus) Ver.-D (SBI) 16.5 I2C Bus Control T5CL8 When the AL is set to “1”, the MST and TRX are cleared to “0” and the mode is switched to a slave receiver mode. Thus, the serial bus interface circuit stops output of clock pulses during data transfer after the AL is set to “1”.
Page 327: Data Transfer Of I2C Bus
T5CL8 16.6 Data Transfer of I C Bus 16.6.1 Device initialization For initialization of device, set the ACK in SBICRA to “1” and the BC to “000”. Specify the data length to 8 bits to count clocks for an acknowledge signal. Set a transfer frequency to the SCK in SBICRA. Next, set the slave address to the SA in I2CAR and clear the ALS to “0”...
Page 328: When The Mst Is "1" (Master Mode)
16. Serial Bus Interface(I2C Bus) Ver.-D (SBI) 16.6 Data Transfer of I2C Bus T5CL8 16.6.3.1 When the MST is “1” (Master mode) Check the TRX and determine whether the mode is a transmitter or receiver. When the TRX is “1” (Transmitter mode) Test the LRB.
Page 329: When The Mst Is "0" (Slave Mode)
T5CL8 To make the transmitter terminate transmit, clear the ACK to “0” before reading data which is 1- word before the last data to be received. A serial bus interface circuit does not generate a clock pulse for the acknowledge signal by clearing ACK. In the interrupt routine of end of transmission, when the BC is set to “001”...
Page 330: Stop Condition Generation
16. Serial Bus Interface(I2C Bus) Ver.-D (SBI) 16.6 Data Transfer of I2C Bus T5CL8 Check the AL (Bit3 in the SBISRB), the TRX (Bit6 in the SBISRB), the AAS (Bit2 in the SBISRB), and the AD0 (Bit1 in the SBISRB) and implements processes according to conditions listed in " Table 16- 4 Operation in the Slave Mode ".
Page 331: Restart
T5CL8 "1" "1" "0" Stop condition "1" SCL pin SDA pin BB (Read) Figure 16-13 Stop Condition Generation 16.6.5 Restart Restart is used to change the direction of data transfer between a master device and a slave device during transferring data. The following explains how to restart a serial bus interface circuit. Clear “0”...
Page 332 16. Serial Bus Interface(I2C Bus) Ver.-D (SBI) 16.6 Data Transfer of I2C Bus T5CL8 Page 210...
Page 333: Bit Ad Converter (Adc)
T5CL8 17. 10-bit AD Converter (ADC) The T5CL8 have a 10-bit successive approximation type AD converter. 17.1 Configuration The circuit configuration of the 10-bit AD converter is shown in Figure 17-1. It consists of control register ADCCR1 and ADCCR2, converted value register ADCDR1 and ADCDR2, a DA converter, a sample-hold circuit, a comparator, and a successive comparison circuit.
Page 334: Register Configuration
17. 10-bit AD Converter (ADC) 17.2 Register configuration T5CL8 17.2 Register configuration The AD converter consists of the following four registers: 1. AD converter control register 1 (ADCCR1) This register selects the analog channels and operation mode (Software start or repeat) in which to per- form AD conversion and controls the AD converter as it starts operating.
Page 335 T5CL8 AD Converter Control Register 2 ADCCR2 (001DH) IREFON "1" "0" (Initial value: **0* 000*) DA converter (Ladder resistor) connection Connected only during AD conversion IREFON control Always connected 000: 39/fc 001: Reserved 010: 78/fc AD conversion time select 011: 156/fc (Refer to the following table about the con- 100:...
Page 336 17. 10-bit AD Converter (ADC) 17.2 Register configuration T5CL8 Before or during conversion EOCF AD conversion end flag Conversion completed Read only During stop of AD conversion ADBF AD conversion BUSY flag During AD conversion Note 1: The ADCDR2<EOCF> is cleared to "0" when reading the ADCDR1. Therfore, the AD conversion result should be read to ADCDR2 more first than ADCDR1.
Page 337: Function
T5CL8 17.3 Function 17.3.1 Software Start Mode After setting ADCCR1<AMD> to “01” (software start mode), set ADCCR1<ADRS> to “1”. AD conver- sion of the voltage at the analog input pin specified by ADCCR1<SAIN> is thereby started. After completion of the AD conversion, the conversion result is stored in AD converted value registers (ADCDR1, ADCDR2) and at the same time ADCDR2<EOCF>...
Page 338: Register Setting
17. 10-bit AD Converter (ADC) 17.3 Function T5CL8 ADCCR1<AMD> “11” “00” AD conversion start ADCCR1<ADRS> AD convert operation suspended. 1st conversion Conversion operation Conversion result is not stored. 2nd conversion result 3rd conversion result result Indeterminate ADCDR1,ADCDR2 1st conversion result 2nd conversion result 3rd conversion result ADCDR2<EOCF>...
Page 339: Stop/Slow Modes During Ad Conversion
T5CL8 Example :After selecting the conversion time 19.5 µs at 16 MHz and the analog input channel AIN3 pin, perform AD con- version once. After checking EOCF, read the converted value, store the lower 2 bits in address 0009EH nd store the upper 8 bits in address 0009FH in RAM.
Page 340: Analog Input Voltage And Ad Conversion Result
17. 10-bit AD Converter (ADC) 17.5 Analog Input Voltage and AD Conversion Result T5CL8 17.5 Analog Input Voltage and AD Conversion Result The analog input voltage is corresponded to the 10-bit digital value converted by the AD as shown in Figure 17-4. conversion result VAREF...
Page 341: Precautions About Ad Converter
T5CL8 17.6 Precautions about AD Converter 17.6.1 Restrictions for AD Conversion interrupt (INTADC) usage When an AD interrupt is used, it may not be processed depending on program composition. For example, if an INTADC interrupt request is generated while an interrupt with priority lower than the interrupt latch IL15 (INTADC) is being accepted, the INTADC interrupt latch may be cleared without the INTADC interrupt being processed.
Page 342 17. 10-bit AD Converter (ADC) 17.6 Precautions about AD Converter T5CL8 Page 220...
Page 343: Key-On Wakeup (Kwu)
T5CL8 18. Key-on Wakeup (KWU) In the T5CL8 , the STOP mode is released by not only P20( ) pin but also four (STOP0 to INT5 STOP STOP3) pins. When the STOP mode is released by STOP0 to STOP3 pins, the pin needs to be used.
Page 344 18. Key-on Wakeup (KWU) 18.3 Function T5CL8 Also, each level of the STOP0 to STOP3 pins can be confirmed by reading corresponding I/O port data register, check all STOP0 to STOP3 pins "H" that is enabled by STOPCR before the STOP mode is started (Note2,3). Note 1: When the STOP mode released by the edge release mode (SYSCR1<RELM>...
Page 345: Flash Memory
T5CL8 19. Flash Memory T5CL8 has 61440byte flash memory (address: 1000H to FFFFH). The write and erase operations to the flash memory are controlled in the following three types of mode. - MCU mode The flash memory is accessed by the CPU control in the MCU mode. This mode is used for software bug correction and firmware change after shipment of the device since the write operation to the flash memory is available by retaining the application behavior.
Page 346: Flash Memory Control
19. Flash Memory 19.1 Flash Memory Control T5CL8 19.1 Flash Memory Control The flash memory is controlled via the flash memory control register (FLSCR) . Flash Memory Control Register FLSCR (0FFFH) FLSMD BANKSEL (Initial value : 1100 1***) 1100: Disable command sequence execution Flash memory command sequence exe- FLSMD 0011: Enable command sequence execution...
Page 347: Command Sequence
T5CL8 19.2 Command Sequence The command sequence in the MCU and the serial PROM modes consists of six commands (JEDEC compatible), as shown in Table 19-2. Addresses specified in the command sequence are recognized with the lower 12 bits (excluding BA, SA, and FF7FH used for security program). The upper 4 bits are used to specify the flash memory area, as shown in Table 19-3.
Page 348: Chip Erase (All Erase)
19. Flash Memory 19.2 Command Sequence T5CL8 A maximum of 30 ms is required to erase 4 kbytes. The next command sequence cannot be executed until the erase operation is completed. To check the completion of the erase operation, perform read operations repeat- edly for data polling until the same data is read twice from the same address in the flash memory.
Page 349: Toggle Bit (D6)
T5CL8 It takes a maximum of 40 µs to set security program in the flash memory. The next command sequence can- not be executed until this operation is completed. To check the completion of the security program operation, perform read operations repeatedly for data polling until the same data is read twice from the same address in the flash memory.
Page 350: Access To The Flash Memory Area
19. Flash Memory 19.4 Access to the Flash Memory Area T5CL8 19.4 Access to the Flash Memory Area When the write, erase and security program are set in the flash memory, read and fetch operations cannot be per- formed in the entire flash memory area. Therefore, to perform these operations in the entire flash memory area, access to the flash memory area by the control program in the BOOTROM or RAM area.
Page 351 T5CL8 Example :After chip erasure, the program in the RAM area writes data 3FH to address F000H. : Disable interrupts (IMF←"0") (FLSCR),00111000B : Enable command sequence execution. IX,0F555H IY,0FAAAH HL,0F000H ; #### Flash Memory Chip erase Process #### (IX),0AAH : 1st bus write cycle (IY),55H : 2nd bus write cycle (IX),80H...
Page 352: How To Write To The Flash Memory By Executing A User Write Control Program In The Ram Area (In The Mcu Mode)
19. Flash Memory 19.4 Access to the Flash Memory Area T5CL8 19.4.2 Flash Memory Control in the MCU mode In the MCU mode, write operations are performed by executing the control program in the RAM area. Before execution of the control program, copy the control program into the RAM area or obtain it from the external using the communication pin.
Page 353 T5CL8 Example :After sector erasure (E000H-EFFFH), the program in the RAM area writes data 3FH to address E000H. : Disable interrupts (IMF←"0") (WDTCR2),4EH : Clear the WDT binary counter. (WDTCR1),0B101H : Disable the WDT. (FLSCR),00111000B : Enable command sequence execution. IX,0F555H IY,0FAAAH HL,0E000H...
Page 354 19. Flash Memory 19.4 Access to the Flash Memory Area T5CL8 Page 232...
Page 355: Serial Prom Mode
T5CL8 20. Serial PROM Mode 20.1 Outline The T5CL8 has a 2048 byte BOOTROM (Mask ROM) for programming to flash memory. The BOOTROM is available in the serial PROM mode, and controlled by TEST, BOOT and pins. Communica- RESET tion is performed via UART. The serial PROM mode has seven types of operating mode: Flash memory writing, RAM loader, Flash memory SUM output, Product ID code output, Flash memory status output, Flash memory eras- ing and Flash memory security program setting.
Page 356: Serial Prom Mode Setting
20. Serial PROM Mode 20.3 Serial PROM Mode Setting T5CL8 20.3 Serial PROM Mode Setting 20.3.1 Serial PROM Mode Control Pins To execute on-board programming, activate the serial PROM mode. Table 20-2 shows pin setting to activate the serial PROM mode. Table 20-2 Serial PROM Mode Setting Setting TEST pin...
Page 357: Example Connection For On-Board Writing
T5CL8 T5CL8 VDD(4.5 V to 5.5 V) Serial PROM mode TEST MCU mode pull-up BOOT / RXD1 (P01) XOUT TXD1 (P02) External control RESET Figure 20-2 Serial PROM Mode Pin Setting Note 1: For connection of other pins, refer to " Table 20-3 Pin Function in the Serial PROM Mode ". 20.3.3 Example Connection for On-Board Writing Figure 20-3 shows an example connection to perform on-board wring.
Page 358: Activating The Serial Prom Mode
20. Serial PROM Mode 20.3 Serial PROM Mode Setting T5CL8 20.3.4 Activating the Serial PROM Mode The following is a procedure to activate the serial PROM mode. " Figure 20-4 Serial PROM Mode Timing " shows a serial PROM mode timing. 1.
Page 359: Interface Specifications For Uart
T5CL8 20.4 Interface Specifications for UART The following shows the UART communication format used in the serial PROM mode. To perform on-board programming, the communication format of the write controller must also be set in the same manner. The default baud rate is 9600 bps regardless of operating frequency of the microcontroller. The baud rate can be modified by transmitting the baud rate modification data shown in Table 1-4 to T5CL8.
Page 360 20. Serial PROM Mode 20.4 Interface Specifications for UART T5CL8 Table 20-5 Operating Frequency and Baud Rate in the Serial PROM Mode Reference Baud Rate 76800 62500 57600 38400 31250 19200 9600 (bps) Baud Rate Modification (Note 3) Data Ref. Fre- Baud Rating quency...
Page 361: Operation Command
T5CL8 20.5 Operation Command The eight commands shown in Table 20-6 are used in the serial PROM mode. After reset release, the T5CL8 waits for the matching data (5AH). Table 20-6 Operation Command in the Serial PROM Mode Command Data Operating Mode Description Setup...
Page 362 20. Serial PROM Mode 20.6 Operation Mode T5CL8 6. Flash memory status output mode The status of the area from FFE0H to FFFFH, and the security program condition are output as 7-byte code. The external controller reads this code to recognize the flash memory status. 7.
Page 363: Flash Memory Erasing Mode (Operating Command: F0H)
T5CL8 20.6.1 Flash Memory Erasing Mode (Operating command: F0H) Table 20-7 shows the flash memory erasing mode. Table 20-7 Flash Memory Erasing Mode Transfer Data from the External Transfer Data from T5CL8 to Transfer Byte Baud Rate Controller to T5CL8 the External Controller 1st byte Matching data (5AH)
Page 364 20. Serial PROM Mode 20.6 Operation Mode T5CL8 2. The 5th byte of the received data contains the command data in the flash memory erasing mode (F0H). 3. When the 5th byte of the received data contains the operation command data shown in Table 20-6, the device echoes back the value which is the same data in the 6th byte position of the received data (in this case, F0H).
Page 365: Flash Memory Writing Mode (Operation Command: 30H)
T5CL8 20.6.2 Flash Memory Writing Mode (Operation command: 30H) Table 20-8 shows flash memory writing mode process. Table 20-8 Flash Memory Writing Mode Process Transfer Data from External Controller Transfer Data from T5CL8 to Transfer Byte Baud Rate to T5CL8 External Controller 1st byte Matching data (5Ah)
Page 366 20. Serial PROM Mode 20.6 Operation Mode T5CL8 Description of the flash memory writing mode 1. The 1st byte of the received data contains the matching data. When the serial PROM mode is acti- vated, T5CL8 (hereafter called device), waits to receive the matching data (5AH). Upon reception of the matching data, the device automatically adjusts the UART’s initial baud rate to 9600 bps.
Page 367 T5CL8 record, the external controller judges whether the transmission is completed correctly by receiving the checksum sent by the device. 14. After transmitting the checksum, the device waits for the next operation command data. Note 1: Do not write only the address from FFE0H to FFFFH when all flash memory data is the same. If only these area are written, the subsequent operation can not be executed due to password error.
Page 368: Ram Loader Mode (Operation Command: 60H)
20. Serial PROM Mode 20.6 Operation Mode T5CL8 20.6.3 RAM Loader Mode (Operation Command: 60H) Table 20-9 shows RAM loader mode process. Table 20-9 RAM Loader Mode Process Transfer Data from External Control- Transfer Data from T5CL8 to Transfer Bytes Baud Rate ler to T5CL8 External Controller...
Page 369 T5CL8 T5CL8 Note 8: If an error occurs during the reception of a password address or a password string, stops UART com- T5CL8 munication and enters the halt condition. In this case, initialize by the pin and reactivate the RESET serial PROM mode.
Page 370: Flash Memory Sum Output Mode (Operation Command: 90H)
20. Serial PROM Mode 20.6 Operation Mode T5CL8 20.6.4 Flash Memory SUM Output Mode (Operation Command: 90H) Table 20-10 shows flash memory SUM output mode process. Table 20-10 Flash Memory SUM Output Process T5CL8 Transfer Data from External Control- Transfer Data from Transfer Bytes Baud Rate T5CL8...
Page 371: Product Id Code Output Mode (Operation Command: C0H)
T5CL8 20.6.5 Product ID Code Output Mode (Operation Command: C0H) Table 20-11 shows product ID code output mode process. Table 20-11 Product ID Code Output Process T5CL8 Transfer Data from External Controller Transfer Data from Transfer Bytes Baud Rate T5CL8 External Controller 1st byte Matching data (5AH)
Page 372 20. Serial PROM Mode 20.6 Operation Mode T5CL8 5. After sending the checksum, the device waits for the next operation command data. Page 250...
Page 373: Flash Memory Status Output Mode (Operation Command: C3H)
T5CL8 20.6.6 Flash Memory Status Output Mode (Operation Command: C3H) Table 20-12 shows Flash memory status output mode process. Table 20-12 Flash Memory Status Output Mode Process T5CL8 Transfer Data from External Con- Transfer Data from Transfer Bytes Baud Rate T5CL8 troller to External Controller...
Page 374: Flash Memory Security Program Setting Mode (Operation Command: Fah)
20. Serial PROM Mode 20.6 Operation Mode T5CL8 20.6.7 Flash Memory security program Setting Mode (Operation Command: FAH) Table 20-13 shows Flash memory security program setting mode process. Table 20-13 Flash Memory security program Setting Mode Process T5CL8 Transfer Data from External Con- Transfer Data from Transfer Bytes Baud Rate...
Page 375 T5CL8 this case, FAH). If the 5th byte does not contain the operation command data, the device enters the halt condition after transmitting 3 bytes of operation command error code (63H). 4. The 7th through m’th bytes of the transmitted and received data contain the same data as in the flash memory writing mode.
Page 376: Error Code
20. Serial PROM Mode 20.7 Error Code T5CL8 20.7 Error Code When detecting an error, the device transmits the error code to the external controller, as shown in Table 20-14. Table 20-14 Error Code Transmit Data Meaning of Error Data 62H, 62H, 62H Baud rate modification error.
Page 377: Calculation Data
T5CL8 20.8.2 Calculation data The data used to calculate the checksum is listed in Table 20-15. Table 20-15 Checksum Calculation Data Operating Mode Calculation Data Description Even when a part of the flash memory is written, the checksum Flash memory writing mode of the entire flash memory area (1000H to FFFH) is calculated.
Page 378: Intel Hex Format (Binary)
20. Serial PROM Mode 20.9 Intel Hex Format (Binary) T5CL8 20.9 Intel Hex Format (Binary) 1. After receiving the checksum of a data record, the device waits for the start mark (3AH “:”) of the next data record. After receiving the checksum of a data record, the device ignores the data except 3AH transmitted by the external controller.
Page 379: Password String
T5CL8 RXD pin UART F0H 12H F1H 07H 01H 02H 03H 04H 05H 06H 07H 08H Password string PNSA PCSA Flash memory F012H "08H" becomes the umber of Compare passwords F107H F108H F109H F10AH 8 bytes F10BH F10CH Example PNSA = F012H F10DH PCSA = F107H Password string = 01H,02H,03H,04H,05H...
Page 380: Product Id Code
20. Serial PROM Mode 20.11 Product ID Code T5CL8 20.11Product ID Code The product ID code is the 13-byte data containing the start address and the end address of ROM. Table 20-17 shows the product ID code format. Table 20-17 Product ID Code Format T5CL8 Data Description...
Page 381 T5CL8 Flash memory security Security program is disabled. RPENA program status Security program is enabled. The status from FFE0H All data is FFH in the area from FFE0H to FFFFH. BLANK to FFFFH. The value except FFH is included in the area from FFE0H to FFFFH. Some operation commands are limited by the flash memory status code 1.
Page 382: Specifying The Erasure Area
20. Serial PROM Mode 20.13 Specifying the Erasure Area T5CL8 20.13Specifying the Erasure Area In the flash memory erasing mode, the erasure area of the flash memory is specified by n−2 byte data. The start address of an erasure area is specified by ERASTA, and the end address is specified by ERAEND. If ERASTA is equal to or smaller than ERAEND, the sector erase (erasure in 4 kbyte units) is executed.
Page 383: Flowchart
T5CL8 20.14Flowchart Page 261...
Page 384: Uart Timing
20. Serial PROM Mode 20.15 UART Timing T5CL8 20.15UART Timing Table 20-19 UART Timing-1 (VDD = 4.5 to 5.5 V, fc = 2 to 16 MHz, Topr = -10 to 40°C) Minimum Required Time Parameter Symbol Clock Frequency (fc) At fc = 2 MHz At fc = 16 MHz 465 µs 58.1 µs...
Page 385: Input/Output Circuit
T5CL8 21. Input/Output Circuit 21.1 Control pins The input/output circuitries of the control pins are shown below. T5CL8 Control Pin Input/Output Circuitry Remarks Osc.enable Resonator connecting pins (high frequency) Input Ω = 1.2 M (typ.) XOUT Output Ω =0.5 k (typ.) XOUT XTEN...
Page 386: Input/Output Ports
21. Input/Output Circuit 21.2 Input/Output Ports T5CL8 21.2 Input/Output Ports Port Input/Output Circuitry Remarks Initial "High-Z" Data output Tri-state I/O Hysteresis input Ω Disable R = 100 (typ.) Pin input Initial "High-Z" Sink open drain output High current output Data output Ω...
Page 387 T5CL8 Port Input/Output Circuitry Remarks Initial "High-Z" Analog input Data output Output latch input Tri-state I/O Ω R = 100 (typ.) Disable Pin input Key-on Wakeup Initial "High-Z" Analog input Data output Tri-state I/O Ω Output latch input R = 100 (typ.) Disable Pin input...
Page 388 21. Input/Output Circuit 21.2 Input/Output Ports T5CL8 Page 266...
Page 389: Electrical Characteristics
T5CL8 22. Electrical Characteristics 22.1 Absolute Maximum Ratings The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user.
Page 390: Operating Conditions
22. Electrical Characteristics 22.1 Absolute Maximum Ratings T5CL8 22.2 Operating Conditions The Operating Conditions shows the conditions under which the device be used in order for it to operate normally while maitaining its quality. If the device is used outside the range of Operating Conditions (power supply voltage, operating temperature range, or AC/DC rated values), it may operate erratically.
Page 391: Serial Prom Mode
T5CL8 22.2.3 Serial PROM mode = 0 V, Topr = -10 to 40 °C) Parameter Symbol Pins Condition Unit Supply voltage NORMAL1, 2 modes × 0.70 Except hysteresis input ≥ 4.5 V Input high voltage × 0.75 Hysteresis input × 0.30 Except hysteresis input ≥...
Page 392: Dc Characteristics
22. Electrical Characteristics 22.1 Absolute Maximum Ratings T5CL8 22.3 DC Characteristics = 0 V, Topr = -40 to 85 °C) Parameter Symbol Pins Condition Typ. Unit Hysteresis voltage Hysteresis input – – TEST = 5.5 V, V = 5.5 V/0 V TEST µA Input current...
Page 393 T5CL8 Note 8: The circuit of a power supply must be designed such as to enable the supply of a peak current. This peak current causes the supply voltage in the device to fluctuate. Connect a bypass capacitor of about 0.1µF near the power supply of the device to stabilize its operation.
Page 394: Ad Characteristics
22. Electrical Characteristics 22.1 Absolute Maximum Ratings T5CL8 22.4 AD Characteristics = 0.0 V, 4.5 V ≤ V ≤ 5.5 V, Topr = -40 to 85 °C) Paramete Symbol Condition Typ. Unit - 1.0 Analog reference voltage – AREF Power supply voltage of analog control circuit ∆...
Page 395: Ac Characteristics
T5CL8 22.5 AC Characteristics = 0 V, 4.5 V ≤ V ≤ 5.5 V, Topr = -40 to 85°C) Parameter Symbol Condition Typ. Unit NORMAL1, 2 modes 0.25 – IDLE0, 1, 2 modes µs Machine cycle time SLOW1, 2 modes 117.6 –...
Page 396: Recommended Oscillating Conditions
22. Electrical Characteristics 22.8 Handling Precaution T5CL8 22.7 Recommended Oscillating Conditions XTOUT XOUT XTIN (1) High-frequency Oscillation (2) Low-frequency Oscillation Note 1: To ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. Because these factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will actually be mounted.
Page 397: Package Dimensions
T5CL8 23. Package Dimensions LQFP64-P-1010-0.50D Rev 01 Unit: mm Page 275...
Page 398 23. Package Dimensions T5CL8 Page 276...
Page 399 This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C (LSI). Toshiba provides a variety of development tools and basic software to enable efficient software development. These development tools have specifications that support advances in microcomputer hardware (LSI) and can be used extensively.
Page 401 TC94B14MFG TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC94B14MFG SiP(System in Package) LSI of; Single-Chip Digital Servo Processor incorporating CD Head Amplifier/Compression AudioDecoder and 16Mbit DRAM for ESP(Electrical Shock Proof) function. The TC94B14MFG is a single chip processor which incorporates the following functions: CD Head amplifier, EFM synchronous signal separation protection interpolation,...
Page 402 TC94B14MFG [Digital servo processor section] • Capable of decoding text data (CD-TEXT mode 4). • Capable of performing sync pattern detection, sync signal protection and interpolation securely. • Built-in EFM demodulation circuit and sub code demodulation circuit • Has a jitter absorbing capacity be switched among ±6 frames and ±22 frames. •...
Page 403 TC94B14MFG Pin Layout and Block Diagram (Top View) Pin Layout (Top View) TEST1 TC94B14MFG (Top View) 2010-01-12...
Page 404 TC94B14MFG Pin Descriptions 1.1 Pin Descriptions Symbol Description Remarks Default DSP VCO - EFM and PLCK Phase difference VCOI signal output pin. 3 state output 3AI/F (DSP VCO control voltage inputr pin.) CD-DSP-Power supply for 3.3V RF RVDD3 amplifier core and PLL circuit Connect capacitor according SLCo EFM slice level output pin...
Page 405 TC94B14MFG Symbol Description Remarks Default Focus Error signal / Sub beam add signal FSMONIT 3AI/F output pin(monitor pin/GND) RFZi RF ripple zero-cross signal Input pin 3AI/F RFRP RF ripple signal output pin. 3AI/F Bulit-in serises R=500Ω. Tracking error signal output pin. Connect to VRo by 3AI/F capacitor.
Page 406 TC94B14MFG Symbol Description Remarks Default DVSS3R Grounding pin for 3.3V Muiti-Bit DAC circuit R channel audio output pin of Audio DAC. 3AI/F DVDD3R Power supply pin for 3.3V Audio DAC circuit. DVDD3L Power supply pin for 3.3V Audio DAC circuit. L channel audio output pin of Audio DAC 3AI/F DVSS3L...
Page 407 TC94B14MFG Symbol Description Remarks Default Connect to GND by 0.1uF VDD3 Power Supply pin for 3.3V Digital circuit Microprocessor I/F data input/output pin 0 CMOS Port BUS0 Schmitt input 3I/F Microprocessor I/F data input/output pin 1 CMOS Port BUS1 Schmitt input 3I/F Microprocessor I/F data input/output pin 2 CMOS Port...
Page 408 TC94B14MFG Note 2: This IC does not have a power-on reset circuit. Keep the /RST pin low until crystal oscillation becomes sufficiently stable with the voltage on each power supply pin risen to a level within the rated range. Once crystal oscillation is stable, keep /RST low for another 10 or more crystal oscillation cycles before driving /RST high.
Page 409 TC94B14MFG 1.2 Pin Assinment Table 1) Audio DSP Audio DSP Pin No Symbol Note AUDIO AUDIO MCKo ZDET -OUT Pio0 Pio0 －－－－－－ Pio1 Pio1 ST_REQ －－－－－ Pio2 Pio2 GATE －－－...
Page 410 TC94B14MFG 2. Initialization method Figure 2-1 shows the power-on and initialization sequences of the TC94B14MFG. (Note) /SRMSTB,VDDM1 and VDD1 should be supplied at the same time within 100ms. Characteristics Symbol Typ. ⎯ VDD3 rise time 1 tvd1 0 ms 100ms ⎯...
Page 411 TC94B14MFG 3. Standby Functions The TC94B14MFG supports SRAM standby modes. When portable or in-vehicle units are on standby, using this mode can reduce waste in battery power consumption. 3-1. Standby mode After shutting down all supply voltages except for VDDM1 (pin 74), making the /SRAMSTB pin (pin 73) low makes it possible to put the built-in 1 Mbit SRAM alone on standby.
Page 412 TC94B14MFG 4. Absolute Maximum rating (Unless otherwise specified, Reference=Ground, Ta=25 °C ) Characteristics Symbol Rating Unit Characteristics VDD3 -0.3~3.8 Supply voltage VDD1 -0.3~2.0 -0.3~VDD3 + 0.3 VIN3 Input voltage VIN1 -0.3~+3.9 Power Dissipation 2674 Operating temperature °C Topr -20~85 Tstg Storage temperature -55 ∼...
Page 413 TC94B14MFG 5. Electrical characteristics 5-1 RF core section (Unless otherwise specified, VDD3 =RVDD3 = AVDD3 = XVDD3 = DVDD3L = DVDD3R = 3.3 V, VDD1-2 = VDDM1 = 1.5V , Ta = 25°C) Test Characteristics Symbol Test Condition Typ. Unit Circuit Power supply voltage Guaranteed-operation...
Page 414 TC94B14MFG Test Characteristics Symbol Test Condition Typ. Unit Circuit AGC+RFEQ section (AGCi → RFEQo) RFGC = 80h ⎯ ⎯ −0.7 Voltage gain 1(Note 2) V1AGC RFGC = B0h ⎯ ⎯ Voltage gain 2(Note 2) ⎯ f = 100 kHz V2AGC RFGC = 7Fh ⎯...
Page 415 TC94B14MFG Test Characteristics Symbol Test Condition Typ. Unit Circuit FE section (FPi1/FPi2 (FNi1/FNi2) → FEi) FEOGAINi = 0000 ⎯ −0.5 ⎯ VA11FE f = 1kHz, CMD: Voltage gain & variable GVSW = 1 range 1 (CD-DA mode) FEOGAINi = 1111 ⎯...
Page 416 TC94B14MFG Test Characteristics Symbol Test Condition Typ. Unit Circuit TE section (TPi (TNi) → TEi) TEOGAINi = 0000 ⎯ ⎯ f = 1 kHz, TEBC = Voltage gain & variable VA11TE range 1 00h, CMD: GVSW TEOGAINi = 1111 ⎯ ⎯...
Page 417 TC94B14MFG Test Characteristics Symbol Test Condition Typ. Unit Circuit RFRP section (RFRPi → RFRP) RFRPGi = 00 ⎯ ⎯ Voltage gain 1 V1RP RFRPGi = 01 ⎯ ⎯ Voltage gain 2 V2RP ⎯ RFRPI input amp gain RFRPGi = 10 ⎯...
Page 418 TC94B14MFG Test Characteristics Symbol Test Condition Typ. Unit Circuit SBAD section (TPi (TNi) → SBAD) f = 1kHz, SBADGAINi = 0000 ⎯ −2.5 ⎯ Voltage gain 1 TEBC = 00h V1SB (CD-DA mode) CMD: GVSW = 1 SBADGAINi = 1111 ⎯...
Page 419 TC94B14MFG 5.2 DSP core section 5-2-1 DC characteristics (Unless otherwise specified, VDD3 = A VDD3 = DVDD3L/R = XVDD3 = RVDD3 = 3.3 V, VDD1 = VDDM1 = 1.5V , Ta = 25°C) Test Characteristics Symbol Test Condition Typ. Unit Circuit VDD3 RVDD3...
Page 420 TC94B14MFG Test Characteristics Symbol Test Condition Typ. Unit Circuit Pins listed at (#3) in the following table. Output resistance integrated at pin kΩ Pins listed at (#4 and #5) in the following table. = 1.6 V, OFF,V /SRMSTB (73pin) = “L” ⎯...
Page 421 TC94B14MFG 5.3 AC Characteristic 5-3-1 MCU I/F Pararell Mode /CCEN tBHW tBLW ＢＵＣＫ BUSi tSZ1 tBUCK BUSi Test Characteristics Symbol Test Condition Typ. Unit Circuit /CCE = “H” pulse width Data disable time tSZ1 /CCE, BUCK delay time BUCK-to-/CEE delay time BUCK cycle time tBUCK...
Page 422 TC94B14MFG 5-3-3 Audio I/F(LRCKi/o,BCKi/o,AIN/OUT) Test Characteristics Symbol Test Condition Typ. Unit Circuit LRCKi Setup time fs = 44.1 kHz, BCKi = 64 fs AIN Setup time fs = 44.1 kHz, BCKi = 64 fs AIN Holdtime fs = 44.1 kHz, BCKi = 64 fs = 8 pF, fs = 44.1 kHz, BCKo Clock cycle BCKO...
Page 423 TC94B14MFG 5-3-3 DATA, CLCK Input/Output timing (1) CLCK input mode Test Characteristics Symbol Test Condition Typ. Unit Circuit “H” level Clock pulse width “ L ” l e v e l Input set-up time CLCK Input mode Transfer time (1) “L”...
Page 424 TC94B14MFG 5-3-4 SBSY, SBOK Input/Output timing Test Characteristics Symbol Test Condition Typ. Unit Circuit “ H ” l e v e l tpLH1 Transfer time (1) SBSY “ L ” l e v e l tpHL1 “ H ” l e v e l tpLH2 Transfer time (2) SBOK...
Page 425 TC94B14MFG 5.4 Analog Circuit Characteristics 5-4-1 AD Converter Test Test Condition Typ. Unit Characteristics Circuit Resolution 176.4 176.4 Sampling frequency SBAD(RFDC) 88.2 RFRP 176.4 0.15 × 0.85 × = 0 V Conversation input range = 3.3 V VDD3 5-4-2. DA Converter (Focus and Tracking Sections) Test Test Condition Typ.
Page 426 TC94B14MFG 5-4-5. TEZI Signal Comparator Test Test Condition Typ. Unit Characteristics Circuit Input range ±50 Hysteresis voltage reference 5-4-6. RFZI Signal Comparator Test Test Condition Typ. Unit Characteristics Circuit Input range Hysteresis voltage reference ±50 5-4-7. Data Slicer Circuit (1) Comparator Test Test Condition Typ.
Page 427 TC94B14MFG 5-4-10 Audio DAC Characteristics Test Characteristics Symbol Test Condition Typ. Unit Circuit ⎯ ⎯ Lo,Ro pin output impedance kΩ 1 kHz sine wave, THD + N (1) ⎯ −88 −80 full scale input. Noise distortion factor 10 kHz sine wave, THD + N (2) ⎯...
Page 428 TC94B14MFG Package LQFP80-P-1212-0.50F Weight : 0.6 g (Typical) 2010-01-12...
Page 429 TC94B14MFG About solderability, following conditions were confirmed • Solderability (1) Use of Sn-37Pb solder Bath · solder bath temperature = 230°C · dipping time = 5 seconds · the number of times = once · use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath ·...
Page 430 TC94B14MFG RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively “Product”) without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA’s written permission, reproduction is permissible only if reproduction is without alteration/omission.

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Cem2100 Cem2100/98

Philips CEM2100/00 Service Manual

2 Operational Description

3 Interrupt Control Circuit

4 Special Function Register (SFR)

5 I/O Ports

6 Watchdog Timer (WDT)

7 Time Base Timer (TBT)

8 Bit Timercounter 1 (TC1)

9 Bit Timer/Counter2 (TC2)

10 Bit Timercounter (TC3, TC4)

11 Bit Timercounter (TC5, TC6)

12 Asynchronous Serial Interface (UART1 )

13 Asynchronous Serial Interface (UART2 )

14 Synchronous Serial Interface (SIO1)

15 Synchronous Serial Interface (SIO2)

16 Serial Bus Interface(I2C Bus) Ver.-D (SBI)

17 Bit AD Converter (ADC)

18 Key-On Wakeup (KWU)

19 Flash Memory

20 Serial PROM Mode

21 Input/Output Circuit

22 Electrical Characteristics

23 Package Dimensions

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