Introduction

Interest in neuromorphic computing has been steadily increasing in recent years, due to its potential to circumvent the Von Neumann bottleneck which arises from the extra energy and time required to transport data between memory and processor units during computation1,2. Spearheaded by improvements in resistive random access memory (RRAM), researchers have attempted to mimic biological neuron and synapse operation by using artificial versions of these elements known as memristors3. In memristors, the operations of both non-volatile memory storage and low-power computing are integrated in one device, taking advantage of the computing strengths of a neural system, namely pattern recognition and unstructured data sorting4. RRAM may be used to implement multiple resistance states and thus serve as trainable synapses in neural networks5,6,7. However, as the field of memristors, RRAM, and neuromorphic computing evolves, the ability to tune the memristive resistance, switching speed, cycling endurance, among other performance criteria, at the atomic scale will be important as device architectures evolve and potentially require devices with different performance capabilities closely integrated together. Control over these performance parameters of memristors at the atomic scale will become critically important to the success of neuromorphic computing2,3,4,8,9,10,11.

Memristors12,13 are two-terminal devices typically consisting of an Ohmic and a Schottky electrode sandwiching a thin insulator, featuring a pinched hysteresis of resistance1 realized through the bipolar switching of two different serially connected resistors or a double-layer (M1/M2) dielectric oxide film. Alternatively, a unipolar memristor is normally comprised of two Schottky interfaces on either side of a thin insulator. The mobile species in the switching layer, typically oxygen vacancies (VO), can be driven back and forth in the M1/M2 film to create a conductive filament (CF). In this switching mechanism, a positive bias (SET) creates an electric field that in conjunction with joule heating causes VO from the vacancy rich M2 layer to diffuse through the higher quality dielectric M1 layer and form a CF, setting the memristor to the low resistance state (LRS). The opposite effect occurs when applying a negative voltage (RESET) and the CF is ruptured through VO diffusion and the memristor is reset to the high resistance state (HRS). Unipolar resistors experience the same CF formation to switch their resistance states, but SET and RESET may occur at both positive and negative bias voltages assisted by a compliance current.

Since the pioneering work by S. Williams in demonstration of the first Pt/TiO2/TiOx/Ti memristor1, many dielectric materials have been studied for memristors using both physical vapor deposition (PVD) such as sputtering, evaporation, and chemical vapor deposition (CVD) such as atomic layer deposition (ALD). A myriad of metal-oxides1,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28 have been utilized for their compatibility with common electrodes selected to form Ohmic and Schottky contacts, their CMOS compatibility, and their high level of performance in memristors29. On/off (defined as HRS/LRS) ratios in the 102–103 range are acceptable for memristor operation, but many memristors have demonstrated higher on/off ratios up to 105–10630,31,32. Some memristors have achieved switching speeds as low as ~100 ps33, though typical memristors show switching speeds in the ~10 ns range3, and low-power switching as low as 115 fJ34. The read/write endurance of the devices has also been observed as high as 1012 cycles17.

In current memristors, VO are a part of many other defects present in the M1/M2 structure as the stack is often fabricated purposely as a “poor oxide” to facilitate CF formation. However, the lack of control of other unwanted defects has serious consequences such as electric leakage and charge traps that in turn impact memristor parameters including M1/M2 thickness, endurance, switching speed/power, on/off ratio, etc. The most sensitive mechanism leading to defect formation in M1/M2 bilayer is the defective metal–insulator interfacial layer (IL). A defective IL can extend the defective microstructure into the M1/M2 layers grown on top and add a defective section to the entire oxide stack through a series connection. Consequently, M1/M2 films are typically made with large thicknesses in the range of 4–12 nm or more to prevent electrical leakage35,36,37,38,39. A defective metal-insulator IL can be caused via formation of native metal oxide and other defects on the metal surface due to the exposure of metal to air or oxygen in ex vacuo processes, difficulties in precise stoichiometric control of metal oxide composition, and formation of growth defects. Even in ALD M1/M2 made in vacuo, poor nucleation and island growth of the initial ALD cycles on metals such as Pt, Au, Pd often leads to a so-called incubation layer or defective metal–insulator IL29,40,41,42,43. Besides the detrimental effect on memristor performance, the presence of unintended defects in M1/M2 makes it difficult to precisely determine memristive switching and conduction mechanisms due to the wide range in M1/M2 thicknesses to accommodate the leakage issue, and large nonuniformity due to lack of defect control at atomic scales, resulting in evidence of numerous conduction mechanisms (Schottky emission44, Poole–Frenkel emission45, trap assisted tunneling46, direct tunneling47, or a combination of mechanisms46,48) and switching mechanisms (though primarily CF formation29,49,50 in metal oxides). Therefore, elimination of the unintended defects in the M1/M2 stack is crucial to tuning of the VO concentration for ultrathin memristor in a controllable manner.

This work explores atomic tuning of ultrathin Al2O3 memristors using an in vacuo ALD process by controllably introducing VO from the “pristine” limit of ALD-Al2O3 grown on Al as an ideal insulator with a negligible metal-insulator IL as we demonstrated recently in Josephson tunnel junctions and capacitors of ultrathin (sub-nm to sub-5 nm) ALD-Al2O3 tunnel barriers and dielectric films51,52,53,54. Specifically, we have shown that a negligible metal–insulator IL would lead to an enhanced ALD-Al2O3 tunnel barrier height (Eb also known as conduction band minimum) by up to 80% from ~ 1.0 eV for its counterpart grown on a defective native AlOx IL51. Furthermore, the Eb is thickness independent without an IL as the ALD-Al2O3 tunnel barrier thickness is varied from 0.11 to 1.1 nm. These, together with the hard dielectric breakdown demonstrated confirms that ultrathin ALD-Al2O3 on Al electrode is indeed a pristine dielectric. If the VO required for memristive switch could be introduced with control at an atomic-scale, the resulting memristors may have fully tunable device parameters by eliminating other unwanted defects.

In order to dope ALD-Al2O3 with VO, a density functional theory (DFT) study was carried out, which revealed that doping Mg in Al2O3 can: (1) lower the Fermi energy of Al2O3 and hence make it more insulating for higher HRS; and (2) lower the VO formation energy to promote VO formation. Experimentally, the atomically controlled Mg doping was explored using in vacuo ALD through artificial stacking of ALD-MgO and ALD-Al2O3 atomic layers with the desired number of ALD-MgO layers in selected locations. Remarkably, tunability of the on/off ratio in the range of 10–104 has been obtained in the M1/M2 thickness range of 1.2–2.4 nm. With the addition of each atomic oxide layer to the M1/M2 stack, we show that the HRS and on/off ratio increase exponentially, confirming that tunneling is the primary conduction mechanism when the device is in HRS. Therefore, this result illustrates a promising approach for atomic-scale tuning of memristors.

Results

DFT simulations of VO doping of pristine Al2O3 for memristors

Figure 1a shows schematically the defects typically formed in a memristor with a M1/M2 stack, in which the M1 layer is intended to be a higher quality insulator while M2 is a “poorer” quality dielectric intended to have more VO. The presence of other unintended defects including interstitials, vacancies of metals, nonuniform VO clusters, and various growth defects implies that the formation of CFs may be highly nonuniform during the memristor SET/RESET operation. In particular, some of these defects may lead to formation of leakage channels and large CFs, which can lead to poor endurance and prevent the achievement of ultrathin memristors with atomic tunability. Figure 1b shows an ultrathin Al2O3 pristine dielectric on an Al electrode obtained using in vacuo ALD with a negligible metal-insulator IL (similar to the tunnel barriers we reported for tunnel junctions and dielectric for capacitors)51,54, in which there are insufficient VO for proper memristive switching. By introducing VO with atomic control (Fig. 1b), atomically tunable ultrathin memristors could be achieved.

Fig. 1: Concept of atomically tuned memristors.
figure 1

a Hypothetical distribution of oxygen vacancies (VO) and other defects in the M1(oxide)/M2(defective oxide) stack of a memristor formed using conventional physical vapor deposition or atomic layer deposition, and b the atomically controlled oxygen vacancy doping from a pristine insulating oxide to allow tunable memristive switching in ultrathin memristors.

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In order to explore the atomic doping of pristine Al2O3, DFT simulations at the hybrid functional level were carried out. Among candidates analyzed, Mg-doping was revealed to be beneficial for memristor applications. In Fig. 2, we have plotted the calculated formation energy as a function of Fermi level (between the valence band maximum and the conduction band minimum) for (a) Al rich and (b) O rich conditions, for native defects (VO, aluminum vacancy (VAl), and aluminum interstitial (Ali)) and all Mg related defects (Mg substituting on Al (MgAl) or O (MgO) sites and Mg interstitials (Mgi)). The slope of the lines indicates the charge state of each defect. These formation energy diagrams shed light on the role of Mg doping, as the requirement of charge neutrality will determine the actual position of the Fermi level. In the absence of Mg, the native defects with lowest formation energy, and thus those that are most likely to form, are VAl, VO, and Ali. These will lead to a Fermi level position within the gray area (Fig. 2a, Al rich conditions) or vertical dashed line (Fig. 2b, O rich). Once Mg is added, the likely Fermi level position will shift towards the valence band maximum, as indicated by the arrows and the solid vertical lines. Note that these are the results for the two extremes of chemical potentials, namely Al rich and O rich. In typical ALD growth, neither of these conditions is representative. To better mimic ALD growth conditions, we set the O chemical potential to −0.65 eV in Fig. 2c55. Again, the same behavior is observed: doping with Mg, which acts as a deep acceptor, lowers the Fermi level during growth. This downward shift has two important consequences: (1) a lower Fermi level indicates that the Mg-doped Al2O3 will be more insulating and thus more resistive in the HRS, as confirmed later by our experimental measurements, and (2) at these lower Fermi levels the formation energy of VO is lower, indicating that more VO will be formed. VO are typically double donors in binary oxides (and confirmed by our calculations), implying that their formation energy will be lower for lower Fermi levels. At the same time oxides are usually unintentionally n-type doped56. This lower Fermi level would render the material more insulating by compensating for the presence of donor defects. Both are desirable to improve the performance of Al2O3-based memristors.

Fig. 2: Density functional theory simulation of MgO doping effect.
figure 2

The defect formation energy as function of the Fermi level for native and Mg-related defects in Al2O3 for chemical potentials corresponding to a Al-rich, b O-rich, and c an oxygen chemical potential (µ0) of −0.65 eV (to mimic atomic layer deposition growth conditions).

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Atomically-controlled VO doping guided by DFT simulations

Experimentally, Mg doping in Al2O3 may be achieved by insertion of an MgO atomic layer into Al2O3 atomic layer stacks grown on Al. Since ALD growth can truly occur layer by layer by carefully controlling the metal-insulator interface and ALD conditions, the MgO/Al2O3 atomic layer stacks obtained using in vacuo ALD allow atomic-scale controlled VO doping53,57. Figure 3 illustrates a few examples including a stack of: 17 Al2O3 atomic layers (Fig. 3a, row i), 14 Al2O3 atomic layers with 3 MgO atomic layers inserted at 3rd, 6th, and 9th layer positions above the Al electrode at the bottom (Fig. 3b, row i), 16 Al2O3 atomic layers with 1 MgO atomic layer inserted at the 1st layer position immediately on the Al electrode (Fig. 3c, row i), and 14 Al2O3 atomic layers with 3 MgO atomic layers inserted at the 1st, 4th and 7th layer positions above the Al electrode (Fig. 3d, row i). It should be noted that all four samples have the same M1/M2 stack thickness of ~1.9 nm (17 total ALD cycles at ~0.11 nm/cycle for MgO and Al2O3 atomic layers) to allow a direct comparison of memristor performance. Without MgO, negligible VO and other defects are expected in the pristine Al2O3 atomic layer stack (Fig. 3a, row ii), which is confirmed in the representative in vacuo scanning tunneling spectroscopy (STS) dI/dV spectrum shown in Fig. 3a, row iii with a large Eb of 1.79 eV and hard dielectric breakdown. In the memristive SET/RESET operation on this device, no sustainable memristive switches were observed except a permanent dielectric breakdown (Fig. 3a, row iv), which is consistent with the STS observation and anticipated for a pristine dielectric. This result also confirms that the M1/M2 layer for memristors differs from the tunnel barriers since the former requires charge carriers (or VO) while the latter requires pristine insulators without mobile charge carriers.

Fig. 3: Design of atomically tuned memristors.
figure 3

In row i, diagrams of atomic layer deposition memristor makeups totaling 17 atomic layers (17 C) in M1(oxide)/M2(defective oxide) stacks are shown. These memristors are comprised of: a 17 Al2O3 atomic layers, b 3 MgO atomic layers in the M1 at the 3rd, 6th, and 9th position from Al electrode at the bottom, c one MgO layer as the M2 layer in the 1st position above Al electrode, and d 3 MgO layers at the 1st, 4th, and 7th position, with the first one serving as the M2. In row ii, diagrams of the expected vacancy distribution in a–d are shown. In row iii, representative scanning tunneling spectroscopy dI/dV curves are shown in log scale to demonstrate local density of states in the a–d samples. In row iv characteristic memristor I–V curves of each device in a–d are displayed showing either early failure or consistent performance.

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By inserting 3 MgO atomic layers at 3rd, 6th, and 9th layer positions above the Al electrode at the bottom (Fig. 3b, row i), VO are introduced in the Al2O3 atomic layers nearby (Fig. 3b, row ii). This is illustrated in the in vacuo STS dI/dV spectrum (Fig. 3b, row iii) including the rounding of the spectrum’s conduction band onset from that of a pristine insulator and slightly reduced Eb to 1.70 eV as compared to the case without doping in Fig. 3a. This VO doping is critical since a few memristive switches were indeed observed (Fig. 3b, row iv) despite low endurance and device yield. In our previous study, the nucleation of the ALD-MgO on Al was found to be more frustrated than ALD-Al2O353,57, which means we may purposely insert a single ALD-MgO atomic layer as the M2 layer on the Al electrode for increased VO amount40,58, followed with deposition of the subsequent M1 layer (Fig. 3c, row i). In this sample, the doped VO are primarily localized near the ohmic metal–insulator IL (Fig. 3c, row ii). Figure 3c, row iii shows a slight dip in Eb of the sample down to ~1.38 eV illustrating the increased carrier doping in the M1/M2. However, unlike those samples with no M2 layer from Fig. 3a, b, the sample with one ALD-MgO atomic layer in M2 shows sustainable memristive switching (Fig. 3c, row iv). Note that the sample in Fig. 3c, row i differs from that in Fig. 3a, row i in the 1 MgO inserted at the 1st layer position above the Al electrode. The memristive switch enabled by this 1 MgO atomic layer, in contrast to straight dielectric breakdown without the MgO, indicates the importance of VO doping near the metal–insulator interface, or the so-called M2 layer. The device in Fig. 3d, row i contains 1 MgO atomic layer in M2, and 2 MgO layers in the M1 Al2O3 stack. The combination of the VO doping in both M1 and M2 layers using the MgO atomic layer insertion leads to a more comprehensive VO doping effect, but similar overall barrier quality as seen in Fig. 3d, row iii, which shows a representative Eb of ~1.38 eV as well. The benefit of this combination is illustrated in the sustainable switching between HRS and LRS (Fig. 3d, row iv) and high device yield ~100%. It should be noted that both samples in Fig. 3b, d, row i have 3 MgO layers. The difference in their electronic structures revealed from the in vacuo STS study indicates the number and location of the inserted MgO atomic layers are both important to atomic tuning of memristor parameters.

Figure 4 shows the results of high-resolution transmission electron microscopy (HRTEM) and energy dispersive X-ray spectroscopy (EDS) taken on a memristor with the same Al2O3 and MgO atomic layer stacking shown in Fig. 3d. The inset of Fig. 4a exhibits the TEM sample extracted using focus ion beam (FIB) from the memristors device. Figure 4a exhibits the cross-sectional HRTEM view of the memristor. Between the Al (top) and Pd (bottom) electrodes, the Al2O3/MgO atomic layer stack of approximately ~2 nm in thickness, which is consistent to the ~1.9 nm thickness expected for the total 17 Al2O3 and MgO atomic layers (~0.11 nm/layer) in this sample, can be clearly seen. Figure 4b exhibits a set of peaks in the HRTEM mode line profile across the Al2O3/MgO atomic layer stack thickness. Each peak in Fig. 4b represents an atomic layer in the Al2O3 and MgO atomic layers stack while the valleys are the respective spacing between the neighboring atomic layers. The Al and Pd electrodes are primarily amorphous, which is expected since both metals were deposited at room temperature. However, some crystallites randomly embedded in Pd have been identified. On these crystallites, the 0.39 nm d-spacing indeed corresponds to the (100) spacing for Pd. The Al2O3/MgO atomic layer stack is amorphous. Figure 4b presents a line profile of the HRTEM image across the Al2O3/MgO atomic layer stack. Interestingly, the presence of the 17 Al2O3 and MgO atomic layers is confirmed by the peaks in the profile with an average inter-peak separation of around 0.1 nm as expected, which means the Al2O3/MgO atomic layer stack was grown layer-by-layer in in vacuo ALD. Figure 4c presents the EDS elemental distributions of Al and Mg across the Al2O3/MgO atomic layer stack, which reveals that the MgO atomic layers are located at the uppermost section of the Al2O3/MgO region as anticipated from the ALD growth shown in Fig. 3d. The EDS results identify the presence of Mg in approximately 1.5 at%, which is less than expected, but agrees with EDS limitations59,60. The EDS results are mostly semi-quantitative, and the main finding is that Mg is in the expected region of the Al2O3/MgO atomic layer stack that is also confirmed in the chemical analysis profile (Fig. 4c, d). The individual EDS maps (Fig. 4e) show the areas of prevalence for Pd, Mg, and Al more clearly. This result clearly demonstrates the presence of Mg, Al, and Pd along the areas expected. It should particularly noted that the layered structure of the Al2O3/MgO atomic layer stack grown in in vacuo ALD process is revealed from the HRTEM/EDS analysis.

Fig. 4: Electron microscopy analysis of memristor microstructure.
figure 4

Transmission Electron Microscopy (TEM) analysis of the memristors architecture for case d in Fig. 3. The images represent: a the actual memristor architecture in High Resolution (HRTEM) mode. The inset in a is the focus ion beam lamella (or the TEM Sample) showing the memristors highlighted with an arrow, b the profile for the 17 atomic layer deposition (ALD) deposited Al2O3 and MgO atomic layers using HRTEM mode where the peaks are attributed to the atomic layers while the valleys, the interstitial space between the neighboring layers. Each of the 17 layers is identified by a number, c the zoom-out view of the memristor in bright field mode, d the similar area to c under energy dispersive X-ray spectroscopy (EDS) mode showing the presence of the main memristor elements of Mg, Al, and Pd, as well as e independent EDS maps for these key elements.

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Design of M1 layer for atomically tunable memristors

Figure 5a, b compare two memristors with 3 MgO atomic layers inserted in 1st, 4th, and 7th layer positions (similar to that in Fig. 3d, row i) while the total M1/M2 thicknesses are 20 C (2.2 nm) and 14 C (1.5 nm) respectively. Considering the two devices both have 1 C MgO in the M2 layer and 2 MgO layers in M1 at the same positions, the major differences between the two devices are in their M1 layer thicknesses through the addition of Al2O3 atomic layers. The two devices exhibit the anticipated hysteretic I–V curves which differ quantitatively in their HRS and hence on/off ratio values due to the M1 layer thicknesses. Indeed, the HRS values for the 20 and 14 C memristors are 3.98 MΩ and 17.4 kΩ respectively while the LRS values are comparable. This results in an on/off of ~104 for the 20 C memristor and ~20 for the 14 C one.

Fig. 5: Tunability of memristor properties by M1/M2 thickness.
figure 5

Diagrams of memristors with an M2 layer of 1 C MgO (~0.11 nm thick) structure with total M1(oxide)/M2(defective oxide) layer thickness of a 20 C, and b 14 C, respectively. Five repeated current/voltage (IV) sweeps of c a 20 C, and d a 14 C memristor. e High resistance state (blue), low resistance state (red), and on/off ratio (black) values along with f SET and RESET voltages as a function of the atomic layer numbers in M1/M2 stack with the similar architecture shown in Fig. 5a, b. Error bars in e were produced from the standard error of multiple device measurements. Error in the SET/RESET voltages of f were a result of the weighted standard deviation of SET/RESET voltages across multiple devices.

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To further understand the effect of the M1 layer thickness on the memristor parameters, the HRS, LRS, on/off, and SET/RESET voltage values of memristors with a total M1/M2 layer thickness varied in the range of 11–22 C, or equivalently the M1 thickness varied from 10 to 21 C (all devices have 1 MgO layer as the M2), are illustrated in Fig. 5e, f, respectively. The HRS (blue) and on/off ratio (black) exhibit monotonic increase with thickness and peak at M1/M2 thickness = 20 C (Fig. 5e). In the semi-log scale, this trend shows a linear curve, indicating they depend on the M1 thickness exponentially and indicate the “tunneling” nature of the memristive HRS conduction. This observation is important as the first demonstration of a quantitative tunability of the memristor parameters by varying the dielectric thickness. For example, the on/off ratio is tunable in the range of 10–104 as the M1/M2 layer thickness is varied between 11 and 22 C (1.2 and 2.4 nm). At larger thicknesses, a drop in HRS and on/off ratio can be observed. Meanwhile, LRS remains more or less constant in almost the entire thickness range likely due to the LRS consisting of series CF and wire resistances, except an upturn for 22 C, suggesting the CF formation may be incomplete. While the mechanism responsible for the HRS decrease at larger thickness above the HRS peak requires more systematic investigation, we hypothesize, based on the trends in both HRS and LRS at the large M1 thickness on the right of the HRS peak, that CF formation/annihilation may become difficult or incomplete above a critical thickness. This argument is plausible considering the tunnel mechanism of memristors revealed in Fig. 5e. In fact, the tunnel barrier thickness is typically in the range of 1–2 nm due to an exponential decrease in tunneling probability with the barrier thickness61,62,63.

Figure 5f, displays the average SET and RESET voltages of the memristors shown in Fig. 5e. A fairly constant SET voltage of 1.0–1.5 V and RESET voltage of −2.0 to −3.5 V were observed on these devices. These values are in the range typical of metal-oxides cataloged in research, which has shown a wide range for SET (0.70–3.0 V) and RESET (−0.70 to −3.5 V) voltages29,64,65. SET and RESET voltages are typically more dependent on diffusivity and switching pulse programming parameters (compliance current, pulse length, etc.) and mostly independent of material selection in metal oxides66,67,68,69. A possible explanation for the slight deviation from the trend with the 11 C thick sample, is that it was possible to SET at a lower voltage due to the much lower HRS (~103 Ω) compared to the next point in the set (~104 Ω). With the added HRS and on/off ratio with increased M1 layer thickness, it is apparent that this layer is the primary provider of resistance in the resistive switching mechanism in these devices.

Effect of metal–insulator IL on memristor performance

It should be noted that all devices in Fig. 5 have 1 MgO atomic layer as the M2 in the M1/M2 stack. In order to understand the difference made by this ALD-M2 layer from an M2 layer made with other methods, another set of memristors was fabricated with an ALD-Al2O3 M1 layer on a defective aluminum oxide M2 formed through oxygen diffusion into an Al electrode (Th–AlOx) under controlled oxygen pressure and exposure time at room temperature. The microstructure of the Th–AlOx is schematically shown in Fig. 1a and a nonuniform distribution of VO in the form of atomic defects and clusters and other defects are anticipated. Such a nonideal defect structure is held responsible for the tunnel barrier leakage when Th–AlOx thickness is <0.6 nm, and low barrier height Eb « 1.0 eV51. This is in contrast to the atomic VO in the ALD-MgO M2 layer. The defective Th–AlOx M2 layer has a direct impact on the quality of the ALD-M1 layer grown on top by extending the defective structure into M1, which in turn affects the Eb of the M1 as shown schematically in Fig. 6a, b. This argument is confirmed in the in vacuo STS study of the electronic structures of the ALD-M1 layers on the two kinds of the M2 layers. Figure 6c shows a representative STS dI/dV spectrum taken on the M1 consisting of 2 MgO layers inserted on the 4th and 7th layer positions in 6 Al2O3 atomic layers on 1 ALD-MgO M2 layer similar to Fig. 3d, row i. The average Eb of 1.45 ± 0.08 eV was observed on this sample. Comparatively, Fig. 6d shows an STS dI/dV spectrum of 10 Al2O3 layers grown on the Th–AlOx M2 layer (~1 nm in thickness) with an average Eb of 0.75 ± 0.01 eV as reported previously51,52. It should be noted that the higher Eb value denotes a higher quality insulator with a lower defect concentration. The much reduced Eb value on the ALD-Al2O3 M1 layer confirms that the defects in the Th–AlOx M2 layer indeed extend into the M1 layer and degrade the dielectric quality of the M1 layer52,70, which in turn impacts the performance of the memristors.

Fig. 6: Effect of tunnel barrier height and Schottky barrier height.
figure 6

Hypothetical barrier energy diagrams at the Pd Schottky interface for a an MgO/Al2O3 memristor, and b an Al2O3/thermal aluminum oxide (Th–AlOx) memristor, where Eb is the tunnel barrier height, VSch is the Schottky barrier height, and ET is the combined total barrier height. Representative scanning tunneling spectroscopy dI/dV spectra of c 9C MgO/Al2O3 mix grown without an interfacial layer (Average Eb = 1.45 ± 0.08 eV) d 10C Al2O3 grown with an interfacial layer (Average Eb = 0.75 ± 0.01 eV). c Comparison of memristor high resistance state (HRS)/low resistance state (LRS) values for memristors with defective oxide (M2) layers composed of ALD-MgO or ThAlOx. d log(RA) fitting used to find total barrier height ET for memristors with the two different M2 layers. Error bars in e are produced from the standard error of multiple measured devices, while data in f is derived using this HRS standard error and propagating the error to the log(RA) value.

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By observing the log-scale plot of both HRS and LRS (Fig. 6e), a trend of exponential increase in HRS with M1/M2 total thickness can be observed over certain ranges for both kinds of memristors with either 1 ALD-MgO M2 (solid blue) or Th-AlOx M2 (open blue) layer. The LRS values remain fairly constant in the former (solid red) while some random jumps are visible on the latter (open red), which are likely due to the randomness and nonuniformity of defects in the Th–AlOx24,35,36,71. An example of this can be seen in both Al2O3 (5 C)/Th-AlOx andAl2O3 (8 C)/Th-AlOx memristors which show almost no change in HRS even with the added 3 C of dielectric in the M1 layer. In fact, the monotonic increasing M1/M2 thickness dependence of HRS occurs only at larger thickness above 17 C total thickness for memristors with on Th–AlOx M2 layer. This is in contrast to the case of the memristors with an ALD-MgO M2 layer, the total M1/M2 layer thickness can be thinner, down to 11 C total with an on/off ratio >10. To our knowledge, this represents the smallest thickness among the ALD-based memristors reported38,72.

In order to quantify the effect of the two kinds of the M2 layers on memristor parameters, we fit the resistance-area (RA) product as function of M1/M2 thickness with the following tunneling current equations:

$$G=\frac{1}{{RA}}\propto {J}_{{{{{{\rm{Tunnel}}}}}}}$$
(1)
$$G={G}_{0}{{{{{\rm{exp }}}}}}\left(-\frac{\sqrt{2{m}_{e}{E}_{T}}}{{\hslash }}d\right)$$
(2)

Where G is the conductance of the device, R is the HRS, A is the device area, me is the mass of the electron, d is the thickness of the tunnel barrier or M1/M2 thickness in memristors, and ET is the total barrier height. The fitting of the memristors with the 1 ALD-MgO M2 layer in Fig. 6f results in an ET of 2.64 ± 0.01 eV, while the fitting of memristors on the Th–AlOx M2 showed significantly lower ET of 1.94 ± 0.01 eV. The higher ET in the former implies a higher specific tunability of HRS per thickness. Note that the fitted ET values in both sets of memristors are higher than the Eb values measured from STS dI/dV spectra. This is different from the tunnel junction case in which the STS measured Eb agrees well with the ET through fitting of device tunneling resistance vs tunnel barrier thickness curve51. This difference can be attributed to the presence of a Schottky barrier (VSch) in memristors while tunnel junctions have two Ohmic contacts, which means ET = VSch + Eb for memristors. Subtracting the Eb from ET for the corresponding memristors results in VSch values of 1.19 ± 0.08 and 1.19 ± 0.01 eV for the memristors on the ALD-MgO and Th–AlOx M2 respectively. This means that the Schottky barrier adds an additional barrier height of 1.19 eV when forming between the Pd electrode and ALD-Al2O3 and works in conjunction with the Eb to provide extremely high resistances at small read voltages. The much higher Eb and hence ET values in the memristors on 1 ALD MgO M2 layer indicates the unintended defects, especially those with high nonuniformity and large dimensions potentially causing leakage, low device yield, and endurance can be minimized in the ALD MgO M2 layer. Furthermore, the comparable electronic structure of the M1 layer grown on top of this ALD MgO M2 layer suggests that the VO doping in this M2 layer is atomic, which does not lead to defective structures on the M1 layer grown on top.

Design of M2 layer for dynamic tunability

Figure 7 compares eight memristors in terms of their HRS (blue), LRS (red), on/off ratios (black) (Fig. 7a), initial (black) and stabilized (blue) HRS (Fig. 7b), and the device yield (Fig. 7c). Memristors 1–7 have the same M1/M2 thickness (17 C or 1.9 nm) but with different numbers and stacking orders of ALD-Al2O3 and ALD-MgO layers grown on an Al electrode (inset of Fig. 7c). Memristor 8 has 8 C of ALD-Al2O3 on the Th–AlOx M2 layer, which is ~1 nm (total M1/M2 thickness also ~1.9 nm). The architectures in these eight memristors were selected to shed light on the role of VO doping by insertion of MgO atomic layers. Samples 1 and 2 used three MgO layers inserted in M1 but not in the M2 layer meaning few VO present at the Ohmic metal-insulator interface. This explains the very low device yields of these two samples (Fig. 7c) and very low endurance (devices failed after the first few memristive switches), signifying that the VO in M1 through the insertion of 3 MgO layers was not sufficient to repeatedly form CFs and instead resulted in permanent dielectric breakdown for a large portion of the devices. The failure suggests that VO in M2 is essential to sustainable formation of CFs during memristive switches. This argument is supported by the considerably improved device yield in Sample 3 that contains 1 MgO in M2 but no MgO in M1. Furthermore, Samples 4–7 have MgO inserted in both M1 and M2 with improved device yield up to 100% in Samples 4, 5, and 7 indicating that it is the combination of the VO doping in both M1 and M2 that enables the sustainable CF formation required for high-performance memristive switches. This indicates that these intermittent ALD-MgO layers in the M1 layer can assist in the formation of CFs as a relay for transferring charge to ionize stabilized neutral VO73. Sample 8 has a similar structure to Sample 3 (with 1 MgO in M2) except with a ~1 nm thick Th–AlOx in M2 with various defects expected as shown schematically in Fig. 1a. The much degraded memristor performance includes reduced HRS, on/off ratio and device yield (~80%) in Sample 8, as compared to Sample 3 as well as Samples 4–7, illustrates the critical importance in controlling unwanted defects in the M1/M2 stack to eliminate their negative impact on CF formation via atomic VO diffusion.

Fig. 7: Effect of M2 layer on memristor performance.
figure 7

a On/Off ratio (black upper), high resistance state (HRS blue middle) and low resistance state (LRS red lower) values, b comparison between initial resistance value and repeatable operating HRS value for various memristors. Device yield for the memristors shown in (c). All have the total M1(oxide) + M2(defective oxide) thickness of 17 C (or ~1.9 nm). Sample 8 has 8 C of atomic layer deposition Al2O3 grown on 1 nm thick defective thermal AlOx (M1/M2 thickness ~1.9 nm). Error bars in a and b are produced from the standard error of multiple measured devices.

Full size image

The location of the inserted MgO layers in M1 may have subtle effects on the memristor performance. For example, Sample 5 has the top-most MgO very close to the Schottky interface which seems to decrease the HRS and on/off as compared to Sample 4 that exhibits the highest HRS and on/off among the eight samples shown in Fig. 7. This means that the Mg-doping in Al2O3 may reduce Vsch due to the Fermi energy reduction and the corresponding shift of the Eb. On the other hand, inserting MgO layers in M1 directly on top of the MgO in M2, such as in Sample 6 (1 MgO in M1 on top of the MgO in M2) and 7 (2 MgO in M1 on top of the MgO in M2), leads to slightly reduced HRS and on/off ratio values in these samples as compared to that in Sample 4. This suggests that the additional MgO layers grown directly on the 1 MgO M2 may increase the VO concentration in M1, making M1 less insulating. Interestingly, these two samples show an R0 value in the 104 Ω range, but when forced to reset during the initial memristive switches, the HRS goes up to the 105 Ω range (Fig. 7b). This is in contrast to the nearly identical R0 and HRS observed in Sample 4. Note that the other samples (except for samples 4, 6, and 7) show lower stabilized HRS after a few initial memristive switches possibly due to dielectric breakdown (Samples 1 and 2), inadequate amount of VO in M1 to support sustainable memristive switches (Sample 3), reduction of the Vsch (Sample 5), and presence of other defects originated from the Th–AlOx M2 (Sample 8). Therefore, the increase from lower R0 to higher stabilized HRS indicates that unlike the other samples in Fig. 7, there may be an excess of VO locally formed at the M1/M2 interface due to Mg-doping by the inserted MgO layers in Samples 6 and 7. Note the increased resistance expected from Mg-doping in pristine Al2O3 predicted from our DFT simulation in Fig. 2 would only occur partially before the localized VO are driven out of the M1/M2 interface by the electric field. This means that the number and location of MgO atomic layers in M1 would allow schemes to dynamically tune the memristor parameters using an electric field. After the dynamic tuning, Samples 6 and 7 have on/off ratio increased by up to an order of magnitude with a device yield of 92% for Sample 6 and 100% for Sample 7.

Conclusion

In conclusion, atomic-scale controlled VO doping of ultrathin pristine Al2O3 has been explored in this work by insertion of MgO atomic layers into Al2O3 atomic layer stacks grown using in vacuo ALD for atomically tunable memristors. Two effects of Mg doping in pristine Al2O3 are revealed in our DFT simulations: reduction of the Fermi energy and hence increase of the resistivity, and increased generation of VO, both desirable for high performance memristors. These two effects are both experimentally confirmed through a comparative study of memristor performance parameters with respect to the number and location of the inserted MgO atomic layers in the MgO/Al2O3 atomic layer stacks. Excitingly, this allows atomically tunable memristors to be achieved. Within the M1/M2 thickness of 1.2–2.4 nm, we show that the HRS can be tuned continuously over three orders of magnitude, leading to an on/off ratio tunable in the range of 10–104 in this thickness range. Furthermore, dynamically tunable on/off ratio by up to one order of magnitude was obtained by arranging the MgO atomic layers at the M1/M2 interface. Finally, an exponentially decreasing tunneling conductance with increasing M1/M2 thickness demonstrates that tunneling is the dominant HRS conduction mechanism of these memristors while the tunnel barrier height ET = Eb + Vsch is determined by the M1/M2 barrier height Eb and the Schottky barrier Vsch meaning that the Schottky and tunnel barriers work in tandem to limit current. In vacuo STS dI/dV characterization has revealed that higher Eb up to 1.45 eV can be obtained in less defective MgO/Al2O3 M1/M2 grown on Al electrode with a negligible metal–insulator interface, in contrast to much lower Eb 0.75 eV when a defective native oxide IL is present. Nevertheless, the Vsch of 1.19 eV can be maintained at the Pd/Al2O3 Schottky interface. This result shows a promising approach for design and fabrication of ultrathin memristors tunable at an atomic scale.

Methods

Sample fabrication

A set of ultrathin memristors with M1/M2 bilayer structure composed of ALD-Al2O3 (ALD-MgO)/ALD-MgAlOx (all ALD memristors) were fabricated using in vacuo ALD. A selected number of ALD-MgO layers were inserted for tuning of the electronic structure and VO concentration of the M1 and M2 layer. The thickness of the M1 layer was varied in the range of (0.6–2.3 nm). Since each ALD-Al2O3 or ALD-MgO atomic layer has a thickness of ~0.11 nm74,75, the resolution of the thickness control is truly atomic via controlling the number of M1 ALD-Al2O3/MgO atomic layers in the range of 5–21. The memristors were defined using a shadow mask to allow 12 memristors to be fabricated on each chip with three different areas of 200 × 200, 200 × 300, and 200 × 400 μm2 for uniformity examination. DC magnetron sputtering of Al and Pd electrodes was carried out in our in vacuo ALD system76 at a base pressure of < 5 × 10−7 Torr, using an Ar plasma (14 mTorr/90 W for Al deposited at 0.5 nm/s, 30 mTorr/45 W for Pd deposited at 1 nm/s, sample distance of ~6 cm). Specifically, the Si/SiO2 (500 nm) substrate was transferred to the sputtering chamber from a load-lock chamber via a transfer rod where an Al electrode was deposited. To make the M1/M2 layer, the ALD chamber was preheated to a temperature of ~225 °C, followed by sample transfer into the ALD chamber and dynamically heating for 25 min with blackbody radiation from the sides of the chamber. Dynamic heating meaning that the sample was not in full thermal equilibrium at the beginning of the ALD, but that the temperature was in the optimal range (starting at ~177 °C)40 and would continue to slowly rise towards 225 °C during further ALD growth. This dynamic heating was found critical to minimizing metal–insulator IL formation at the Al interface caused by excessive heating times needed to reach proper thermal equilibrium51,52,70. The sample was then subjected to alternating 2 s long precursor pulses of H2O and either Trimethyl-Aluminum (TMA) at room temperature or Bis(cyclopentadienyl)magnesium(II) (MgCp2) heated to 100 °C assisted by a flow of 5 SCCM of N2. Between each precursor pulse the ALD chamber was purged for 35 s using N2 and a vacuum pump. The precursor pulses were fully computer controlled to allow ALD-MgO and ALD-Al2O3 atomic layers to be stacked in any order or amount desired. Since each of the Al2O3 and MgO atomic layers is only ~0.1 nm, the doping effect by MgO in Al2O3 in an Al2O3/MgO film of 1–2 nm thickness is expected to be similar to “Mg” uniformly distributed in 3D volume of a bulk MgO-doped Al2O3 sample77. Once the M1/M2 was grown the sample was transferred in vacuo back to a high vacuum chamber to let it cool in a low oxygen environment. Post-cooling, the sample was then removed from vacuum and the 2nd shadow mask was mounted for deposition of the top Pd electrode. For comparison, a set of memristors with 1 nm defective Th–AlOx M2 and ALD M1 were fabricated with total M1/M2 thickness ranging from 1.5 to 3.0 nm. For these samples the main difference was that the sample was allowed to cool post Al deposition, and then placed in the loadlock chamber to undergo oxidation using high purity O2 at ~2 Torr for 520 s resulting in ~1040 Torr s, which is estimated to result in approximately 1 nm of defective Th–AlOx oxide M2 layer51.

Ex Vacuo sample characterization

Electrical measurements of the shadow-mask-fabricated samples were carried out using 25 µm tungsten probes in a probe station in conjunction with an Agilent B1500 semiconductor analyzer. The Pd electrode was grounded while the Al electrode was biased. Initial low voltage (−500 to 500 mV) sweeps of each device fabricated were performed to probe the initial resistance. HRS and LRS values were measured at 100 mV, a point at which the Schottky barrier is still effective. Very slight electroforming appears to be necessary in these devices as their first switch usually requires a slightly higher voltage than the average switching voltage. Electrode resistance from the Pd and Al wires was subtracted, because in normal photomask samples the electrodes would be thick enough so that their resistance would be negligible.

In Vacuo scanning tunneling spectroscopy (STS)

In Vacuo STS was taken using an RHK UHV system at ~10−10 Torr. STS samples were measured by fabricating a half-cell of the memristor structure, i.e., the fabrication steps are all the same except the sample is transferred for examination after the M2/M1 bilayer is grown. Local density of states (LDOS) was proportionately measured through dI/dV spectra collected using a mechanically cleaved PtIr tip by sweeping a DC voltage from 0 to 2.3 V with a lock-in amplifier analyzing the 45 mV 5 kHz AC signal on top of the DC signal. Approximately 60–80 spectra were randomly taken as the films were too sensitive for scanning tunneling microscopy scans. Using two bisquare fits, the intersection of the conduction band and band gap regions are estimated to estimate Eb also known as the barrier height Eb, as well as high-quality ALD coverage rate51,52,57,70,78.

DFT simulation

DFT calculations were performed using projector augmented wave (PAW) potentials79 with the HSE0680 hybrid functional as implemented in the Vienna Ab-initio Simulation Package (VASP)81,82. The mixing parameter was set to 32%55,83. We used a 120-atom supercell with periodic boundary conditions for all the defect calculations. Using a Γ-centered 2 × 2 × 2 k-point grid with a plane wave expansion cutoff of 400 eV, all structures were relaxed until the forces were smaller than 10 meV/Å. The defect formation energies were calculated using the formalism outlined in Freysoldt et al.84. The chemical potentials were limited by the formation of MgAl2O4. Charge state corrections were calculated using the sxdefectalign code85,86.

Focus ion beam (FIB) and high-resolution transmission electron microscopy (HRTEM)

The HRTEM sample was extracted directly from the memristors device using a Helios-ThermoFisher FIB instrument assisted by a Ga ion gun. The scanning transmission electron micrograph (STEM), high-angle annular dark-field imaging (HAADF), and energy dispersive X-ray spectroscopy (EDS) maps were obtained by using the FEI Titan Themis3 system equipped with image and probe aberration corrections and an electron monochromator at 300 kV.